davinci_emac: fix for running with dcache enabled
DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache enabled by default. So we have to take care and flush/invalidate the cache before/after the DMA operations. Please note that the receive buffer alignment to 32 byte boundary comes from the old driver version I don't know if it is really needed or alignment to cache line size is enough. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
This commit is contained in:
Ilya Yanok
Albert ARIBAUD
parent
2f3427ccb9
commit
2aa8720257
drivers/net
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@ -41,6 +41,7 @@
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#include <net.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <linux/compiler.h>
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#include <asm/arch/emac_defs.h>
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#include <asm/io.h>
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#include "davinci_emac.h"
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@ -105,7 +106,8 @@ static volatile emac_desc *emac_rx_active_tail = 0;
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static int emac_rx_queue_active = 0;
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/* Receive packet buffers */
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static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
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static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
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__aligned(ARCH_DMA_MINALIGN);
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#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
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#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
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@ -119,6 +121,26 @@ static u_int8_t num_phy;
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phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
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static inline void davinci_flush_rx_descs(void)
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{
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/* flush the whole RX descs area */
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flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
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EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
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}
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static inline void davinci_invalidate_rx_descs(void)
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{
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/* invalidate the whole RX descs area */
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invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
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EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
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}
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static inline void davinci_flush_desc(emac_desc *desc)
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{
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flush_dcache_range((unsigned long)desc,
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(unsigned long)desc + sizeof(*desc));
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}
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static int davinci_eth_set_mac_addr(struct eth_device *dev)
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{
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unsigned long mac_hi;
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@ -470,7 +492,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
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emac_rx_active_head = emac_rx_desc;
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for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
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rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
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rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)];
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rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
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rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
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rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
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rx_desc++;
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@ -482,6 +504,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
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emac_rx_active_tail = rx_desc;
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emac_rx_queue_active = 1;
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davinci_flush_rx_descs();
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/* Enable TX/RX */
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writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
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writel(0, &adap_emac->RXBUFFEROFFSET);
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@ -639,6 +663,11 @@ static int davinci_eth_send_packet (struct eth_device *dev,
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EMAC_CPPI_SOP_BIT |
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EMAC_CPPI_OWNERSHIP_BIT |
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EMAC_CPPI_EOP_BIT);
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flush_dcache_range((unsigned long)packet,
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(unsigned long)packet + length);
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davinci_flush_desc(emac_tx_desc);
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/* Send the packet */
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writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
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@ -671,6 +700,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
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volatile emac_desc *tail_desc;
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int status, ret = -1;
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davinci_invalidate_rx_descs();
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rx_curr_desc = emac_rx_active_head;
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status = rx_curr_desc->pkt_flag_len;
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if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
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@ -678,6 +709,9 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
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/* Error in packet - discard it and requeue desc */
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printf ("WARN: emac_rcv_pkt: Error in packet\n");
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} else {
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unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
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invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
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NetReceive (rx_curr_desc->buffer,
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(rx_curr_desc->buff_off_len & 0xffff));
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ret = rx_curr_desc->buff_off_len & 0xffff;
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@ -703,6 +737,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
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rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
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rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
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rx_curr_desc->next = 0;
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davinci_flush_desc(rx_curr_desc);
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if (emac_rx_active_head == 0) {
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printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
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@ -720,11 +755,13 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
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tail_desc->next = BD_TO_HW((ulong) curr_desc);
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status = tail_desc->pkt_flag_len;
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if (status & EMAC_CPPI_EOQ_BIT) {
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davinci_flush_desc(tail_desc);
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writel(BD_TO_HW((ulong)curr_desc),
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&adap_emac->RX0HDP);
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status &= ~EMAC_CPPI_EOQ_BIT;
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tail_desc->pkt_flag_len = status;
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}
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davinci_flush_desc(tail_desc);
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}
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return (ret);
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}
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@ -24,8 +24,9 @@
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/* Ethernet Min/Max packet size */
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#define EMAC_MIN_ETHERNET_PKT_SIZE 60
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#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
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/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */
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#define EMAC_PKT_ALIGN 18
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/* Buffer size (should be aligned on 32 byte and cache line) */
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#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
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ARCH_DMA_MINALIGN)
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/* Number of RX packet buffers
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* NOTE: Only 1 buffer supported as of now
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