ARMV7: Add basic gpmc initialization for OMAP4
This patch adds a gpmc_init function for OMAP4 and adds calls to gpmc_init for existing OMAP4 boards: panda and sdp4430 Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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27952014c4
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@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a
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SOBJS += lowlevel_init.o
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COBJS += board.o
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COBJS += mem.o
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COBJS += sys_info.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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@ -0,0 +1,45 @@
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Steve Sakoman <steve@sakoman.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/cpu.h>
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#include <asm/arch/sys_proto.h>
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struct gpmc *gpmc_cfg;
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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/* global settings */
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
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/*
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* Disable the GPMC0 config set by ROM code
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* It conflicts with our MPDB (both at 0x08000000)
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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}
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@ -31,6 +31,51 @@
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gpmc_cs {
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u32 config1; /* 0x00 */
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u32 config2; /* 0x04 */
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u32 config3; /* 0x08 */
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u32 config4; /* 0x0C */
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u32 config5; /* 0x10 */
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u32 config6; /* 0x14 */
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u32 config7; /* 0x18 */
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u32 nand_cmd; /* 0x1C */
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u32 nand_adr; /* 0x20 */
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u32 nand_dat; /* 0x24 */
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u8 res[8]; /* blow up to 0x30 byte */
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x4];
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u32 irqstatus; /* 0x18 */
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u32 irqenable; /* 0x1C */
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u8 res3[0x20];
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u32 timeout_control; /* 0x40 */
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u8 res4[0xC];
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u32 config; /* 0x50 */
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u32 status; /* 0x54 */
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u8 res5[0x8]; /* 0x58 */
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struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
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u8 res6[0x14]; /* 0x1E0 */
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u32 ecc_config; /* 0x1F4 */
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u32 ecc_control; /* 0x1F8 */
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u32 ecc_size_config; /* 0x1FC */
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u32 ecc1_result; /* 0x200 */
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u32 ecc2_result; /* 0x204 */
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u32 ecc3_result; /* 0x208 */
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u32 ecc4_result; /* 0x20C */
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u32 ecc5_result; /* 0x210 */
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u32 ecc6_result; /* 0x214 */
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u32 ecc7_result; /* 0x218 */
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u32 ecc8_result; /* 0x21C */
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u32 ecc9_result; /* 0x220 */
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};
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/* Used for board specific gpmc initialization */
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extern struct gpmc *gpmc_cfg;
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res[0xc];
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@ -86,6 +131,9 @@ struct watchdog {
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* GPMC BASE */
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#define GPMC_BASE (OMAP44XX_GPMC_BASE)
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/* I2C base */
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#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
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#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
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@ -62,7 +62,7 @@
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#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
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/* GPMC */
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#define GPMC_BASE 0x50000000
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#define OMAP44XX_GPMC_BASE 0x50000000
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/*
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* Hardware Register Details
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@ -28,6 +28,7 @@ struct omap_sysinfo {
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char *board_string;
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};
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void gpmc_init(void);
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void watchdog_init(void);
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u32 get_device_type(void);
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void invalidate_dcache(u32);
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@ -37,6 +37,8 @@ const struct omap_sysinfo sysinfo = {
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
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gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
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@ -38,6 +38,8 @@ const struct omap_sysinfo sysinfo = {
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP;
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gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
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