x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -17,5 +17,4 @@ obj-y += northbridge.o
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obj-y += report_platform.o
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obj-y += sata.o
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obj-y += sdram.o
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obj-y += usb_ehci.o
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obj-y += usb_xhci.o
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@ -159,9 +159,6 @@ static int bd82x6x_probe(struct udevice *dev)
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/* Cause the SATA device to do its init */
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uclass_first_device(UCLASS_DISK, &dev);
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bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
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bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
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gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
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if (gma_node < 0) {
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debug("%s: Cannot find GMA node\n", __func__);
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@ -1,29 +0,0 @@
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/*
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* From Coreboot
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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void bd82x6x_usb_ehci_init(pci_dev_t dev)
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{
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u32 reg32;
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/* Disable Wake on Disconnect in RMH */
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reg32 = readl(RCB_REG(0x35b0));
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reg32 |= 0x22;
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writel(reg32, RCB_REG(0x35b0));
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debug("EHCI: Setting up controller.. ");
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reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER;
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/* reg32 |= PCI_COMMAND_SERR; */
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x86_pci_write_config32(dev, PCI_COMMAND, reg32);
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debug("done.\n");
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}
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@ -12,6 +12,8 @@
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aliases {
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spi0 = "/pci/pch/spi";
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usb0 = &usb_0;
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usb1 = &usb_1;
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};
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config {
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@ -226,6 +228,16 @@
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u-boot,dm-pre-reloc;
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};
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usb_1: usb@1a,0 {
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reg = <0x0000d000 0 0 0 0>;
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compatible = "ehci-pci";
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};
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usb_0: usb@1d,0 {
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reg = <0x0000e800 0 0 0 0>;
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compatible = "ehci-pci";
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};
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,bd82x6x", "intel,pch9";
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@ -7,7 +7,6 @@
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#ifndef _ASM_ARCH_BD82X6X_H
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#define _ASM_ARCH_BD82X6X_H
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void bd82x6x_usb_ehci_init(pci_dev_t dev);
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void bd82x6x_usb_xhci_init(pci_dev_t dev);
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int gma_func0_init(struct udevice *dev, const void *blob, int node);
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