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da850evm: fix NAND WSTROBE and TA timings 

The current NAND timings, introduced in commit
a3f88293dd da850evm: setup the NAND flash
timings , incorrectly set WSTROBE and TA to 0. A more recent inspection of the
values set by the Linux kernel indicates that these should be set to 1.

Set the WSTROBE and TA field of the EMIFA cycle-count timings configuration to
1 to match the values set by linux.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Stefano Babic <sbabic@denx.de>
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Ben Gardiner 2011-04-20 16:25:06 -04:00 committed by Albert ARIBAUD
parent 264eaa0ea9
commit 24a514c445
1 changed files with 2 additions and 2 deletions
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4
board/davinci/da8xxevm/da850evm.c
View File

@ -179,12 +179,12 @@ int board_init(void)
* Linux kernel @ 25MHz EMIFA * Linux kernel @ 25MHz EMIFA
*/ */
writel((DAVINCI_ABCR_WSETUP(0) | writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(0) | DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) | DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) | DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) | DAVINCI_ABCR_RSTROBE(1) |
DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(0) | DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT), DAVINCI_ABCR_ASIZE_8BIT),
&davinci_emif_regs->ab2cr); /* CS3 */ &davinci_emif_regs->ab2cr); /* CS3 */
#endif #endif