powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Haiying Wang
Kumar Gala
parent
67a719da2e
commit
24995d829a
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@ -69,7 +69,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
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COBJS-$(CONFIG_FSL_CORENET) += liodn.o
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COBJS-$(CONFIG_MP) += mp.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-$(CONFIG_FSL_CORENET) += portals.o
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COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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# various SoC specific assignments
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COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -30,18 +30,13 @@
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR;
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static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
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void setup_portals(void)
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{
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#ifdef CONFIG_FSL_CORENET
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int i;
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/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
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#ifdef CONFIG_PHYS_64BIT
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out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
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#endif
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out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
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for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
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u8 sdest = qp_info[i].sdest;
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u16 fliodn = qp_info[i].fliodn;
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@ -53,6 +48,13 @@ void setup_portals(void)
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/* set frame liodn */
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out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
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}
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#endif
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/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
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#ifdef CONFIG_PHYS_64BIT
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out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
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#endif
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out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
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}
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/* Update portal containter to match LAW setup of portal in phy map */
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@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container,
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static int fdt_qportal(void *blob, int off, int id, char *name,
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enum fsl_dpaa_dev dev, int create)
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{
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int childoff, dev_off, num, ret = 0;
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int childoff, dev_off, ret = 0;
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uint32_t dev_handle;
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#ifdef CONFIG_FSL_CORENET
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int num;
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u32 liodns[2];
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#endif
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childoff = fdt_subnode_offset(blob, off, name);
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if (create) {
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@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
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if (ret < 0)
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return ret;
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#ifdef CONFIG_FSL_CORENET
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num = get_dpaa_liodn(dev, &liodns[0], id);
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ret = fdt_setprop(blob, childoff, "fsl,liodn",
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&liodns[0], sizeof(u32) * num);
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#endif
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} else {
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return childoff;
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}
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@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob)
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
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while (off != -FDT_ERR_NOTFOUND) {
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#ifdef CONFIG_FSL_CORENET
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u32 liodns[2];
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#endif
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const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
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int j, i = *ci;
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@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob)
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if (err < 0)
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goto err;
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#ifdef CONFIG_FSL_CORENET
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liodns[0] = qp_info[i].dliodn;
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liodns[1] = qp_info[i].fliodn;
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@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob)
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&liodns, sizeof(u32) * 2);
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if (err < 0)
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goto err;
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#endif
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i++;
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@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob)
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if (err < 0)
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goto err;
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#ifdef CONFIG_FSL_CORENET
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#ifdef CONFIG_SYS_DPAA_PME
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err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
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if (err < 0)
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@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob)
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#else
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fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
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#endif
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
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char name[] = "fman@0";
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@ -162,7 +162,6 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
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}
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#endif
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#endif
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#ifdef CONFIG_QE
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qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
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@ -170,6 +169,15 @@ void get_sys_info (sys_info_t * sysInfo)
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sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
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#if (CONFIG_SYS_NUM_FMAN) == 2
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sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
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#endif
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#endif
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#endif /* CONFIG_FSL_CORENET */
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#if defined(CONFIG_FSL_LBC)
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#if defined(CONFIG_SYS_LBC_LCRR)
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/* We will program LCRR to this value later */
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@ -1,5 +1,5 @@
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/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob);
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#define SET_QMAN_LIODN(liodn) \
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SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
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CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \
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CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
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CONFIG_SYS_FSL_QMAN_OFFSET, \
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CONFIG_SYS_FSL_QMAN_OFFSET)
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#define SET_BMAN_LIODN(liodn) \
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SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
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CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \
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CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
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CONFIG_SYS_FSL_BMAN_OFFSET, \
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CONFIG_SYS_FSL_BMAN_OFFSET)
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#define SET_PME_LIODN(liodn) \
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SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
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@ -2204,8 +2204,8 @@ typedef struct ccsr_pme {
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#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
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#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
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#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
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#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
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#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
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#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
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#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
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#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
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#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
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@ -2268,10 +2268,10 @@ typedef struct ccsr_pme {
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#define CONFIG_SYS_FSL_CPC_ADDR \
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(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
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#define CONFIG_SYS_FSL_QMAN_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
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#define CONFIG_SYS_FSL_BMAN_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
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#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
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@ -357,6 +357,7 @@
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#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
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/* Qman/Bman */
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
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#define CONFIG_SYS_BMAN_NUM_PORTALS 10
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#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
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#ifdef CONFIG_PHYS_64BIT
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