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ddr: altera: Clean up run_mem_calibrate() 

Clean the function up slightly by using clrsetbits_le32() to flip
bits in registers instead of cryptic bitmasks. Zap condition checking
for PHY_DEBUG_IN_DEBUG_MODE flag, which is never set. Split the
calibration report into separate debug_mem_calibrate() function.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-17 01:20:21 +02:00
parent 9fa9c90e70
commit 23a040c047
1 changed files with 34 additions and 22 deletions
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56
drivers/ddr/altera/sequencer.c
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@ -3448,44 +3448,57 @@ static uint32_t mem_calibrate(void)
return 1; return 1;
} }
static uint32_t run_mem_calibrate(void) /**
* run_mem_calibrate() - Perform memory calibration
*
* This function triggers the entire memory calibration procedure.
*/
static int run_mem_calibrate(void)
{ {
uint32_t pass; int pass;
uint32_t debug_info;
debug("%s:%d\n", __func__, __LINE__); debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */ /* Reset pass/fail status shown on afi_cal_success/fail */
writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status); writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
/* stop tracking manger */ /* Stop tracking manager. */
uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg); clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
phy_mgr_initialize(); phy_mgr_initialize();
rw_mgr_mem_initialize(); rw_mgr_mem_initialize();
/* Perform the actual memory calibration. */
pass = mem_calibrate(); pass = mem_calibrate();
mem_precharge_and_activate(); mem_precharge_and_activate();
writel(0, &phy_mgr_cmd->fifo_reset); writel(0, &phy_mgr_cmd->fifo_reset);
/* Handoff. */
rw_mgr_mem_handoff();
/* /*
* Handoff: * In Hard PHY this is a 2-bit control:
* Don't return control of the PHY back to AFI when in debug mode. * 0: AFI Mux Select
* 1: DDIO Mux Select
*/ */
if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) { writel(0x2, &phy_mgr_cfg->mux_sel);
rw_mgr_mem_handoff();
/*
* In Hard PHY this is a 2-bit control:
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
writel(0x2, &phy_mgr_cfg->mux_sel);
}
writel(ctrlcfg, &sdr_ctrl->ctrl_cfg); /* Start tracking manager. */
setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
return pass;
}
/**
* debug_mem_calibrate() - Report result of memory calibration
* @pass: Value indicating whether calibration passed or failed
*
* This function reports the results of the memory calibration
* and writes debug information into the register file.
*/
static void debug_mem_calibrate(int pass)
{
uint32_t debug_info;
if (pass) { if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__); printf("%s: CALIBRATION PASSED\n", __FILE__);
@ -3524,7 +3537,7 @@ static uint32_t run_mem_calibrate(void)
writel(debug_info, &sdr_reg_file->failing_stage); writel(debug_info, &sdr_reg_file->failing_stage);
} }
return pass; printf("%s: Calibration complete\n", __FILE__);
} }
/** /**
@ -3732,7 +3745,6 @@ int sdram_calibration_full(void)
skip_delay_mask = 0x0; skip_delay_mask = 0x0;
pass = run_mem_calibrate(); pass = run_mem_calibrate();
debug_mem_calibrate(pass);
printf("%s: Calibration complete\n", __FILE__);
return pass; return pass;
} }