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Blackfin: split cache handling out of dma_memcpy() 

Creating a new dma_memcpy() function that skips all cache checks allows us
to use the function in very early init where the cache is not yet setup.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2008-08-07 15:31:13 -04:00
parent d31eb38512
commit 21d6313604
1 changed files with 17 additions and 8 deletions
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25
lib_blackfin/string.c
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@ -134,7 +134,7 @@ int strncmp(const char *cs, const char *ct, size_t count)
* Perhaps we should detect that ? Nowhere do we actually * Perhaps we should detect that ? Nowhere do we actually
* use dma memcpy for those types of lengths though ... * use dma memcpy for those types of lengths though ...
*/ */
static void *dma_memcpy(void *dst, const void *src, size_t count) void dma_memcpy_nocache(void *dst, const void *src, size_t count)
{ {
/* Scratchpad cannot be a DMA source or destination */ /* Scratchpad cannot be a DMA source or destination */
if (((unsigned long)src >= L1_SRAM_SCRATCH && if (((unsigned long)src >= L1_SRAM_SCRATCH &&
@ -143,10 +143,9 @@ static void *dma_memcpy(void *dst, const void *src, size_t count)
(unsigned long)dst < L1_SRAM_SCRATCH_END)) (unsigned long)dst < L1_SRAM_SCRATCH_END))
hang(); hang();
if (dcache_status()) bfin_write_MDMA_S0_CONFIG(0);
blackfin_dcache_flush_range(src, src + count); bfin_write_MDMA_D0_CONFIG(0);
bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
/* Copy sram functions from sdram to sram */ /* Copy sram functions from sdram to sram */
/* Setup destination start address */ /* Setup destination start address */
@ -165,13 +164,23 @@ static void *dma_memcpy(void *dst, const void *src, size_t count)
/* Enable source DMA */ /* Enable source DMA */
bfin_write_MDMA_S0_CONFIG(DMAEN); bfin_write_MDMA_S0_CONFIG(DMAEN);
SSYNC();
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN); bfin_write_MDMA_D0_CONFIG(WNR | DMAEN);
SSYNC();
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN)
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); continue;
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_RUN | DMA_DONE | DMA_ERR);
bfin_write_MDMA_D0_CONFIG(0);
bfin_write_MDMA_S0_CONFIG(0);
}
void *dma_memcpy(void *dst, const void *src, size_t count)
{
if (dcache_status())
blackfin_dcache_flush_range(src, src + count);
dma_memcpy_nocache(dst, src, count);
if (icache_status()) if (icache_status())
blackfin_icache_flush_range(dst, dst + count); blackfin_icache_flush_range(dst, dst + count);