mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards
This involves configuring the SerDes and fixing up the flags and PHY addresses for the TSECs. For Linux we also fix up the device tree. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -15,6 +15,7 @@
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <spd_sdram.h>
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#include <tsec.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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@ -44,6 +45,8 @@ int board_early_init_f(void)
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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@ -62,6 +65,125 @@ int board_early_init_f(void)
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return 0;
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}
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#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
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int board_eth_init(bd_t *bd)
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{
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struct tsec_info_struct tsec_info[2];
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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int num = 0;
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/* New line after Net: */
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printf("\n");
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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printf(CONFIG_TSEC1_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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printf(CONFIG_TSEC2_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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return tsec_eth_init(bd, tsec_info, num);
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}
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static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
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int phy_addr)
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{
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const char *phy_type = "sgmii";
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const u32 *ph;
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int off;
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int err;
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off = fdt_path_offset(blob, alias);
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if (off < 0) {
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printf("WARNING: could not find %s alias: %s.\n", alias,
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fdt_strerror(off));
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return;
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}
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err = fdt_setprop(blob, off, "phy-connection-type", phy_type,
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strlen(phy_type) + 1);
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if (err) {
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printf("WARNING: could not set phy-connection-type for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
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if (!ph) {
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printf("WARNING: could not get phy-handle for %s.\n",
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alias);
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return;
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}
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off = fdt_node_offset_by_phandle(blob, *ph);
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if (off < 0) {
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printf("WARNING: could not get phy node for %s: %s\n", alias,
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fdt_strerror(off));
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return;
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}
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phy_addr = cpu_to_fdt32(phy_addr);
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err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
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if (err < 0) {
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printf("WARNING: could not set phy node's reg for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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}
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static void ft_tsec_fixup(void *blob, bd_t *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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#ifdef CONFIG_TSEC1
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
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#endif
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#ifdef CONFIG_TSEC2
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
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#endif
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}
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#else
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static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
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#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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@ -152,6 +274,7 @@ int checkboard(void)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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ft_tsec_fixup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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@ -382,6 +382,8 @@
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_PHY_ADDR_SGMII 8
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#define TSEC2_PHY_ADDR_SGMII 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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