common/board_f.c: change the macro name and remove it for PPC platforms
For most PPC platforms, they will call the first get_clocks() in init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is then defined to call the second get_clocks(), which should be redundant for PPC. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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5757e06c69
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18fb0e3cae
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@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
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#if defined(CONFIG_BOARD_POSTCLK_INIT)
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board_postclk_init,
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#endif
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#ifdef CONFIG_FSL_CLK
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#ifdef CONFIG_SYS_FSL_CLK
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get_clocks,
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#endif
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#ifdef CONFIG_M68K
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@ -0,0 +1,6 @@
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Freescale system clock options
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- CONFIG_SYS_FSL_CLK
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Enable to call get_clocks() in board_init_f() for
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non-PPC platforms and PCC 8xx platforms such as
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TQM866M and TQM885D.
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@ -17,7 +17,6 @@
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#define CONFIG_BSC9132
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#endif
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#define CONFIG_FSL_CLK
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#define CONFIG_MISC_INIT_R
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#ifdef CONFIG_SDCARD
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@ -10,7 +10,6 @@
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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/*
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* High Level Configuration Options
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@ -9,7 +9,6 @@
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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/*
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* High Level Configuration Options
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@ -16,7 +16,6 @@
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#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
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#define CONFIG_MPC837XERDB 1
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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@ -12,7 +12,6 @@
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#include "../board/freescale/common/ics307_clk.h"
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#ifdef CONFIG_36BIT
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@ -12,7 +12,6 @@
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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@ -15,7 +15,6 @@
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#define CONFIG_PHYS_64BIT
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#endif
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_P1010
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#define CONFIG_E500 /* BOOKE e500 family */
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@ -12,7 +12,6 @@
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#include "../board/freescale/common/ics307_clk.h"
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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@ -15,7 +15,6 @@
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#define CONFIG_PHYS_64BIT
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_PPC_P2041
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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@ -20,7 +20,6 @@
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_PHYS_64BIT
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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@ -20,7 +20,6 @@
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_PHYS_64BIT
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#define CONFIG_ENABLE_36BIT_PHYS
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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@ -29,7 +29,6 @@
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#define CONFIG_T1040QDS
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#define CONFIG_PHYS_64BIT
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
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@ -13,7 +13,6 @@
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#define CONFIG_T104xRDB
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#define CONFIG_PHYS_64BIT
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_E500 /* BOOKE e500 family */
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#include <asm/config_mpc85xx.h>
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@ -13,7 +13,6 @@
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#define CONFIG_FSL_CLK
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#define CONFIG_MMC
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#define CONFIG_USB_EHCI
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#if defined(CONFIG_PPC_T2080)
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@ -14,7 +14,6 @@
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_T2080RDB
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#define CONFIG_FSL_CLK
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#define CONFIG_MMC
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#define CONFIG_USB_EHCI
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#define CONFIG_FSL_SATA_V2
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@ -12,7 +12,6 @@
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#define CONFIG_T4240QDS
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#define CONFIG_PHYS_64BIT
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#define CONFIG_FSL_CLK
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#define CONFIG_FSL_SATA_V2
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#define CONFIG_PCIE4
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@ -13,7 +13,6 @@
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#define CONFIG_T4240RDB
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#define CONFIG_PHYS_64BIT
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_FSL_SATA_V2
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#define CONFIG_PCIE4
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@ -15,7 +15,6 @@
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_FSL_ELBC
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#define CONFIG_PCI
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@ -18,7 +18,7 @@
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_USE_ARCH_MEMSET
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_ARCH_MISC_INIT
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#define CONFIG_DISPLAY_CPUINFO
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@ -44,7 +44,6 @@
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#define CONFIG_P1022
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#define CONFIG_CONTROLCENTERD
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#define CONFIG_MP /* support multiple processors */
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_NO_FLASH
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@ -11,7 +11,6 @@
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#include "../board/freescale/common/ics307_clk.h"
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@ -23,7 +23,6 @@
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#define CONFIG_IDENT_STRING " hrcon 0.01"
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#define CONFIG_FSL_CLK
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_LAST_STAGE_INIT
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@ -11,7 +11,7 @@
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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@ -11,7 +11,7 @@
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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@ -16,7 +16,7 @@ unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
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@ -18,7 +18,7 @@
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unsigned long get_board_sys_clk(void);
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#endif
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ 133333333
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#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
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@ -17,7 +17,7 @@
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_FIT
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@ -14,7 +14,7 @@
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#define CONFIG_MX25
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#define CONFIG_SYS_TEXT_BASE 0x81200000
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#define CONFIG_MXC_GPIO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_TIMER_RATE 32768
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#define CONFIG_SYS_TIMER_COUNTER \
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@ -19,7 +19,7 @@
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#define CONFIG_MX35
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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/* Set TEXT at the beginning of the NOR flash */
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#define CONFIG_SYS_TEXT_BASE 0xA0000000
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@ -18,7 +18,7 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#include <asm/arch/imx-regs.h>
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@ -23,7 +23,7 @@
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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@ -23,7 +23,7 @@
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_OF_LIBFDT
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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/* ATAGs */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_SYSCOUNTER_TIMER
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define CONFIG_SYS_FSL_CLK
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/* Enable iomux-lpsr support */
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#define CONFIG_IOMUX_LPSR
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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#define __CONFIG_H
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#if defined(CONFIG_TWR_P1025)
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#define CONFIG_BOARDNAME "TWR-P1025"
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#define CONFIG_P1025
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#define CONFIG_MX53
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_OF_LIBFDT
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#define CONFIG_MXC_GPIO
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_MACH_TYPE 4146
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/* High Level Configuration Options */
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#define CONFIG_MX35
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#define CONFIG_MX35_HCLK_FREQ 24000000
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#define CONFIG_FSL_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_CACHELINE_SIZE 32
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