x86: ivybridge: Sort out the calls to bridge_silicon_revision()
This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
a5ea3a7d4a
commit
1605b10032
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@ -353,14 +353,13 @@ static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
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return 0;
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}
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static int gma_pm_init_pre_vbios(void *gtt_bar)
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static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
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{
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u32 reg32;
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debug("GT Power Management Init, silicon = %#x\n",
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bridge_silicon_revision());
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debug("GT Power Management Init, silicon = %#x\n", rev);
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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if (rev < IVB_STEP_C0) {
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/* 1: Enable force wake */
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gtt_write(gtt_bar, 0xa18c, 0x00000001);
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gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
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@ -370,14 +369,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
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/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
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reg32 = gtt_read(gtt_bar, 0x42004);
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reg32 |= (1 << 14) | (1 << 15);
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gtt_write(gtt_bar, 0x42004, reg32);
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}
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if (bridge_silicon_revision() >= IVB_STEP_A0) {
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if (rev >= IVB_STEP_A0) {
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/* Display Reset Acknowledge Settings */
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reg32 = gtt_read(gtt_bar, 0x45010);
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reg32 |= (1 << 1) | (1 << 0);
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@ -386,7 +385,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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/* 2: Get GT SKU from GTT+0x911c[13] */
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reg32 = gtt_read(gtt_bar, 0x911c);
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
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if (reg32 & (1 << 13)) {
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debug("SNB GT1 Power Meter Weights\n");
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gtt_write_powermeter(gtt_bar, snb_pm_gt1);
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@ -435,13 +434,13 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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reg32 = gtt_read(gtt_bar, 0xa180);
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reg32 |= (1 << 26) | (1 << 31);
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/* (bit 20=1 for SNB step D1+ / IVB A0+) */
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if (bridge_silicon_revision() >= SNB_STEP_D1)
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if (rev >= SNB_STEP_D1)
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reg32 |= (1 << 20);
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gtt_write(gtt_bar, 0xa180, reg32);
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/* 6a: for SnB step D2+ only */
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if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
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(bridge_silicon_revision() >= SNB_STEP_D2)) {
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if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
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(rev >= SNB_STEP_D2)) {
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reg32 = gtt_read(gtt_bar, 0x9400);
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reg32 |= (1 << 7);
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gtt_write(gtt_bar, 0x9400, reg32);
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@ -453,7 +452,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
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}
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
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reg32 = gtt_read(gtt_bar, 0x907c);
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reg32 |= (1 << 16);
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gtt_write(gtt_bar, 0x907c, reg32);
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@ -505,7 +504,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
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/* 11a: Enable Render Standby (RC6) */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
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/*
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* IvyBridge should also support DeepRenderStandby.
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*
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@ -539,14 +538,14 @@ static int gma_pm_init_pre_vbios(void *gtt_bar)
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return 0;
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}
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int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
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int gma_pm_init_post_vbios(int rev, void *gtt_bar, const void *blob, int node)
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{
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u32 reg32, cycle_delay;
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debug("GT Power Management Init (post VBIOS)\n");
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/* 15: Deassert Force Wake */
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if (bridge_silicon_revision() < IVB_STEP_C0) {
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if (rev < IVB_STEP_C0) {
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gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
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gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
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} else {
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@ -805,6 +804,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
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ulong base;
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u32 reg32;
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int ret;
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int rev;
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/* Enable PCH Display Port */
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writew(0x0010, RCB_REG(DISPBDF));
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@ -813,6 +813,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
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ret = uclass_first_device(UCLASS_NORTHBRIDGE, &nbridge);
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if (!nbridge)
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return -ENODEV;
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rev = bridge_silicon_revision(nbridge);
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sandybridge_setup_graphics(nbridge, dev);
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/* IGD needs to be Bus Master */
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@ -827,7 +828,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
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gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
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debug("GT bar %p\n", gtt_bar);
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ret = gma_pm_init_pre_vbios(gtt_bar);
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ret = gma_pm_init_pre_vbios(gtt_bar, rev);
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if (ret)
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return ret;
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@ -838,7 +839,7 @@ int gma_func0_init(struct udevice *dev, const void *blob, int node)
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debug("BIOS ran in %lums\n", get_timer(start));
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#endif
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/* Post VBIOS init */
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ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
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ret = gma_pm_init_post_vbios(rev, gtt_bar, blob, node);
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if (ret)
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return ret;
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@ -19,23 +19,17 @@
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/sandybridge.h>
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static int bridge_revision_id = -1;
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int bridge_silicon_revision(void)
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int bridge_silicon_revision(struct udevice *dev)
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{
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if (bridge_revision_id < 0) {
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struct cpuid_result result;
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uint8_t stepping, bridge_id;
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pci_dev_t dev;
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struct cpuid_result result;
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u16 bridge_id;
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u8 stepping;
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result = cpuid(1);
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stepping = result.eax & 0xf;
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dev = PCI_BDF(0, 0, 0);
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bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
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bridge_revision_id = bridge_id | stepping;
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}
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return bridge_revision_id;
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result = cpuid(1);
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stepping = result.eax & 0xf;
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dm_pci_read_config16(dev, PCI_DEVICE_ID, &bridge_id);
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bridge_id &= 0xf0;
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return bridge_id | stepping;
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}
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/*
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@ -91,45 +85,45 @@ static void add_fixed_resources(struct udevice *dev, int index)
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}
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}
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static void northbridge_dmi_init(struct udevice *dev)
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static void northbridge_dmi_init(struct udevice *dev, int rev)
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{
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/* Clear error status bits */
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writel(0xffffffff, DMIBAR_REG(0x1c4));
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writel(0xffffffff, DMIBAR_REG(0x1d0));
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/* Steps prior to DMI ASPM */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
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clrsetbits_le32(DMIBAR_REG(0x250), (1 << 22) | (1 << 20),
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1 << 21);
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}
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setbits_le32(DMIBAR_REG(0x238), 1 << 29);
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if (bridge_silicon_revision() >= SNB_STEP_D0) {
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if (rev >= SNB_STEP_D0) {
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setbits_le32(DMIBAR_REG(0x1f8), 1 << 16);
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} else if (bridge_silicon_revision() >= SNB_STEP_D1) {
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} else if (rev >= SNB_STEP_D1) {
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clrsetbits_le32(DMIBAR_REG(0x1f8), 1 << 26, 1 << 16);
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setbits_le32(DMIBAR_REG(0x1fc), (1 << 12) | (1 << 23));
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}
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/* Enable ASPM on SNB link, should happen before PCH link */
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB)
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if ((rev & BASE_REV_MASK) == BASE_REV_SNB)
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setbits_le32(DMIBAR_REG(0xd04), 1 << 4);
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setbits_le32(DMIBAR_REG(0x88), (1 << 1) | (1 << 0));
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}
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static void northbridge_init(struct udevice *dev)
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static void northbridge_init(struct udevice *dev, int rev)
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{
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u32 bridge_type;
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add_fixed_resources(dev, 6);
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northbridge_dmi_init(dev);
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northbridge_dmi_init(dev, rev);
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bridge_type = readl(MCHBAR_REG(0x5f10));
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bridge_type &= ~0xff;
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
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if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
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/* Enable Power Aware Interrupt Routing - fixed priority */
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clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4);
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@ -220,10 +214,13 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev)
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static int bd82x6x_northbridge_probe(struct udevice *dev)
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{
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int rev;
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if (!(gd->flags & GD_FLG_RELOC))
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return bd82x6x_northbridge_early_init(dev);
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northbridge_init(dev);
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rev = bridge_silicon_revision(dev);
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northbridge_init(dev, rev);
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return 0;
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}
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@ -108,7 +108,13 @@
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#define DMIBAR_REG(x) (DEFAULT_DMIBAR + x)
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int bridge_silicon_revision(void);
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/**
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* bridge_silicon_revision() - Get the Northbridge revision
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*
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* @dev: Northbridge device
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* @return revision ID (bits 3:0) and bridge ID (bits 7:4)
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*/
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int bridge_silicon_revision(struct udevice *dev);
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void report_platform_info(struct udevice *dev);
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