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arm, am335x: add some missing registers and defines for lcd and epwm support 

- add missing register defines in struct cm_perpl
  epwmss0clkctrl
  epwmss2clkctrl
  lcdcclkstctrl
- add missing register defines in struct cm_dpll
  clklcdcpixelclk
- add struct pwmss_regs
- add struct pwmss_ecap_regs
- add LCD Controller base LCD_CNTL_BASE
- add PWM0 controller base PWMSS0_BASE

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Heiko Schocher 2013-08-19 16:38:57 +02:00 committed by Tom Rini
parent dafd4db33a
commit 14c0158b18
2 changed files with 41 additions and 1 deletions
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35
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -193,7 +193,8 @@ struct cm_perpll {
unsigned int dcan1clkctrl; /* offset 0xC4 */
unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int resv7[2];
unsigned int epwmss0clkctrl; /* offset 0xD4 */
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
unsigned int resv8[4];
@ -204,6 +205,7 @@ struct cm_perpll {
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
unsigned int cpswclkstctrl; /* offset 0x144 */
unsigned int lcdcclkstctrl; /* offset 0x148 */
};
#else
/* Encapsulating core pll registers */
@ -366,6 +368,8 @@ struct cm_perpll {
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
/* Control Module RTC registers */
@ -505,6 +509,35 @@ struct ctrl_dev {
#define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
#define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
/* PWMSS */
struct pwmss_regs {
unsigned int idver;
unsigned int sysconfig;
unsigned int clkconfig;
unsigned int clkstatus;
};
#define ECAP_CLK_EN BIT(0)
#define ECAP_CLK_STOP_REQ BIT(1)
struct pwmss_ecap_regs {
unsigned int tsctr;
unsigned int ctrphs;
unsigned int cap1;
unsigned int cap2;
unsigned int cap3;
unsigned int cap4;
unsigned int resv1[4];
unsigned short ecctl1;
unsigned short ecctl2;
};
/* Capture Control register 2 */
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
#define ECTRL2_MDSL_ECAP BIT(9)
#define ECTRL2_CTRSTP_FREERUN BIT(4)
#define ECTRL2_PLSL_LOW BIT(10)
#define ECTRL2_SYNC_EN BIT(5)
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */

7
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
View File

@ -58,4 +58,11 @@
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
/* LCD Controller */
#define LCD_CNTL_BASE 0x4830E000
/* PWMSS */
#define PWMSS0_BASE 0x48300000
#define AM33XX_ECAP0_BASE 0x48300100
#endif /* __AM33XX_HARDWARE_AM33XX_H */