Merge branch 'lwmon5-no-ocm'
This commit is contained in:
Stefan Roese
commit
1466ef8db5
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@ -57,7 +57,7 @@ tlbtab:
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#ifdef CFG_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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#endif
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/* TLB-entry for PCI Memory */
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@ -26,10 +26,21 @@
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#include <common.h>
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#include <commproc.h>
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#include <asm/io.h>
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#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
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#if defined(CFG_POST_ALT_WORD_ADDR)
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void post_word_store (ulong a)
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{
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out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
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}
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ulong post_word_load (void)
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{
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return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
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}
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#else /* CFG_POST_ALT_WORD_ADDR */
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void post_word_store (ulong a)
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{
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volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
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@ -41,6 +52,7 @@ ulong post_word_load (void)
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volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
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return *(volatile ulong *) save_addr;
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}
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#endif /* CFG_POST_ALT_WORD_ADDR */
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#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
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@ -636,6 +636,33 @@ _start:
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dcbz r0,r3
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addi r3,r3,32
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bdnz ..d_ag
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/*
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* Lock the init-ram/stack in d-cache, so that other regions
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* may use d-cache as well
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* Note, that this current implementation locks exactly 4k
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* of d-cache, so please make sure that you don't define a
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* bigger init-ram area. Take a look at the lwmon5 440EPx
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* implementation as a reference.
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*/
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msync
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isync
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/* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
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lis r1,0x0201
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ori r1,r1,0xf808
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mtspr dvlim,r1
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lis r1,0x0808
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ori r1,r1,0x0808
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mtspr dnv0,r1
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mtspr dnv1,r1
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mtspr dnv2,r1
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mtspr dnv3,r1
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mtspr dtv0,r1
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mtspr dtv1,r1
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mtspr dtv2,r1
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mtspr dtv3,r1
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msync
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isync
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#endif /* CFG_INIT_RAM_DCACHE */
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/* 440EP & 440GR are only 440er PPC's without internal SRAM */
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@ -1345,6 +1372,31 @@ relocate_code:
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mr r4,r10
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mr r5,r11
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#endif
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#ifdef CFG_INIT_RAM_DCACHE
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/*
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* Unlock the previously locked d-cache
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*/
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msync
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isync
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/* set TFLOOR/NFLOOR to 0 again */
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lis r6,0x0001
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ori r6,r6,0xf800
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mtspr dvlim,r6
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lis r6,0x0000
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ori r6,r6,0x0000
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mtspr dnv0,r6
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mtspr dnv1,r6
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mtspr dnv2,r6
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mtspr dnv3,r6
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mtspr dtv0,r6
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mtspr dtv1,r6
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mtspr dtv2,r6
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mtspr dtv3,r6
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msync
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isync
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#endif /* CFG_INIT_RAM_DCACHE */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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@ -71,15 +71,20 @@
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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/*
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* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
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* the POST_WORD from OCM to a 440EPx register that preserves it's
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* content during reset (GPT0_COM6). This way we reserve the OCM (16k)
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* for logbuffer only.
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*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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/* unused GPT0 COMP reg */
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/*-----------------------------------------------------------------------
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* Serial Port
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@ -1362,8 +1362,6 @@
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#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* Pin Function Control Register 1 */
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#define SDR0_PFC1 0x4101
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#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
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@ -1429,7 +1427,7 @@
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#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
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#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
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#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
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#define GPT0_COMP6 0x00000098
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_USB2D0CR 0x0320
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@ -194,7 +194,7 @@ struct post_test post_list[] =
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"SPR test",
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"spr",
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"This test checks SPR contents.",
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POST_ROM | POST_ALWAYS | POST_PREREL,
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POST_RAM | POST_ALWAYS,
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&spr_post_test,
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NULL,
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NULL,
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