ARM: IXP: Remove actux2 board
The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Marek Vasut
parent
373ee048a8
commit
13e0ee7f9a
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := actux2.o
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@ -1,122 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include "actux2_hw.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* CS1: IPAC-X */
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writel(0x94d10013, IXP425_EXP_CS1);
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/* CS5: Debug port */
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writel(0x9d520003, IXP425_EXP_CS5);
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/* CS6: HW release register */
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writel(0x81860001, IXP425_EXP_CS6);
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/* CS7: LEDs */
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writel(0x80900003, IXP425_EXP_CS7);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
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/* Setup GPIOs for Interrupt inputs */
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
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/* Setup GPIOs for 33MHz clock output */
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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writel(0x011001FF, IXP425_GPIO_GPCLKR);
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udelay(533);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
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ACTUX2_LED1(1);
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ACTUX2_LED2(0);
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ACTUX2_LED3(0);
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ACTUX2_LED4(0);
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return 0;
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}
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/*
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* Check Board Identity
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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puts("Board: AcTux-2 rev.");
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putc(ACTUX2_BOARDREL + 'A' - 1);
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
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return 0;
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}
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information
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* 0 = reserved
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* 1 = Rev. A
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* 2 = Rev. B
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*************************************************************************/
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u32 get_board_rev(void)
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{
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return ACTUX2_BOARDREL;
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}
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void reset_phy(void)
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{
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/* init IcPlus IP175C ethernet switch to native IP175C mode */
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miiphy_write("NPE0", 29, 31, 0x175C);
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}
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@ -1,43 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* hardware register definitions for the AcTux-2 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ACTUX2_HW_H
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#define _ACTUX2_HW_H
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/* 0 = LED off,1 = green, 2 = red, 3 = orange */
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#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
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#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
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#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
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#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
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#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
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#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
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#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPIO_DBGINT 0
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#define CONFIG_SYS_GPIO_ETHINT 1
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#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
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#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
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#define CONFIG_SYS_GPIO_UNUSED4 4
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#define CONFIG_SYS_GPIO_UNUSED5 5
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#define CONFIG_SYS_GPIO_DSR 6 /* Out */
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#define CONFIG_SYS_GPIO_DCD 7 /* Out */
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#define CONFIG_SYS_GPIO_IPAC_INT 8
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#define CONFIG_SYS_GPIO_DBGJUMPER 9
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#define CONFIG_SYS_GPIO_BUTTON1 10
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#define CONFIG_SYS_GPIO_DBGSENSE 11
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#define CONFIG_SYS_GPIO_DTR 12
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#define CONFIG_SYS_GPIO_IORST 13 /* Out */
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#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
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#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
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#endif
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@ -1,99 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
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OUTPUT_ARCH (arm)
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ENTRY (_start)
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SECTIONS
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{
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. = 0x00000000;
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. = ALIGN (4);
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.text : {
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*(.__image_copy_start)
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arch/arm/cpu/ixp/start.o(.text*)
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net/built-in.o(.text*)
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board/actux2/built-in.o(.text*)
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arch/arm/cpu/ixp/built-in.o(.text*)
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drivers/input/built-in.o(.text*)
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. = env_offset;
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common/env_embedded.o(.ppcenv)
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*(.text*)
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}
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. = ALIGN(4);
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.rodata : {
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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}
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. = ALIGN(4);
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.data : {
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*(.data*)
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}
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. = ALIGN(4);
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.got : {
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*(.got)
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}
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. =.;
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. = ALIGN(4);
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.u_boot_list : {
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KEEP(*(SORT(.u_boot_list*)));
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}
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. = ALIGN (4);
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.image_copy_end :
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{
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*(.__image_copy_end)
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}
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.rel_dyn_start :
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{
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*(.__rel_dyn_start)
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}
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.rel.dyn : {
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*(.rel*)
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}
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.rel_dyn_end :
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{
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*(.__rel_dyn_end)
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}
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_end = .;
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/*
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* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
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* __bss_base and __bss_limit are for linker only (overlay ordering)
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*/
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.bss_start __rel_dyn_start (OVERLAY) : {
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KEEP(*(.__bss_start));
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__bss_base = .;
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}
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.bss __bss_base (OVERLAY) : {
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*(.bss*)
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. = ALIGN(4);
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__bss_limit = .;
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}
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.bss_end __bss_limit (OVERLAY) : {
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KEEP(*(.__bss_end));
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}
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.dynsym _end : { *(.dynsym) }
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.dynbss : { *(.dynbss) }
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.dynstr : { *(.dynstr*) }
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.dynamic : { *(.dynamic*) }
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.hash : { *(.hash*) }
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.plt : { *(.plt*) }
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.interp : { *(.interp*) }
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.gnu : { *(.gnu*) }
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.ARM.exidx : { *(.ARM.exidx*) }
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}
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@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris
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Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
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Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
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Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
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Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
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@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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mx1ads arm arm920t - 2014-01-13
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mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
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@ -1,206 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* Configuration settings for the AcTux-2 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_IXP425 1
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#define CONFIG_ACTUX2 1
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#define CONFIG_MACH_TYPE 1480
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_IXP_SERIAL
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds"
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command line configuration. */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#undef CONFIG_CMD_PCI
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#undef CONFIG_PCI
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_KGDB_BAUDRATE 230400
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00400000
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#define CONFIG_SYS_MEMTEST_END 0x00800000
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200, 230400 }
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#define CONFIG_SERIAL_RTS_ACTIVE 1
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/* Expansion bus settings */
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#define CONFIG_SYS_EXP_CS0 0xbd113042
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/* SDRAM settings */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/* 16MB SDRAM */
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#define CONFIG_SYS_SDR_CONFIG 0x3A
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#define PHYS_SDRAM_1_SIZE 0x01000000
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#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
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#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
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#define CONFIG_SYS_DRAM_SIZE 0x01000000
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/* FLASH organization */
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 140
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#define PHYS_FLASH_1 0x50000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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#define CONFIG_BOARD_SIZE_LIMIT 262144
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/* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* no byte writes on IXP4xx */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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|
||||
/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Ethernet */
|
||||
|
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/* include IXP4xx NPE support */
|
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#define CONFIG_IXP4XX_NPE 1
|
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/* NPE0 PHY address */
|
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#define CONFIG_PHY_ADDR 0x00
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/* MII PHY management */
|
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#define CONFIG_MII 1
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/* fixed-speed switch without standard PHY registers on MII */
|
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#define CONFIG_MII_NPE0_FIXEDLINK 1
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#define CONFIG_MII_NPE0_SPEED 100
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#define CONFIG_MII_NPE0_FULLDUPLEX 1
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|
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/* Number of ethernet rx buffers & descriptors */
|
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#define CONFIG_SYS_RX_ETH_BUFFER 16
|
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#define CONFIG_RESET_PHY_R 1
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/* ethernet switch connected to MII port */
|
||||
#define CONFIG_MII_ETHSWITCH 1
|
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|
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#define CONFIG_CMD_DHCP
|
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
|
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#define CONFIG_CMD_PING
|
||||
#undef CONFIG_CMD_NFS
|
||||
|
||||
/* BOOTP options */
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
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#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/*
|
||||
* environment organization:
|
||||
* one flash sector, embedded in uboot area (bottom bootblock flash)
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x2000
|
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
|
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#define CONFIG_SYS_USE_PPCENV 1
|
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|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
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"npe_ucode=50040000\0" \
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"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
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||||
"kerneladdr=50050000\0" \
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"kernelfile=actux2/uImage\0" \
|
||||
"rootfile=actux2/rootfs\0" \
|
||||
"rootaddr=50170000\0" \
|
||||
"loadaddr=10000\0" \
|
||||
"updateboot_ser=mw.b 10000 ff 40000;" \
|
||||
" loady ${loadaddr};" \
|
||||
" run eraseboot writeboot\0" \
|
||||
"updateboot_net=mw.b 10000 ff 40000;" \
|
||||
" tftp ${loadaddr} actux2/u-boot.bin;" \
|
||||
" run eraseboot writeboot\0" \
|
||||
"eraseboot=protect off 50000000 50003fff;" \
|
||||
" protect off 50006000 5003ffff;" \
|
||||
" erase 50000000 50003fff;" \
|
||||
" erase 50006000 5003ffff\0" \
|
||||
"writeboot=cp.b 10000 50000000 4000;" \
|
||||
" cp.b 16000 50006000 3a000\0" \
|
||||
"updateucode=loady;" \
|
||||
" era ${npe_ucode} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
|
||||
"updateroot=tftp ${loadaddr} ${rootfile};" \
|
||||
" era ${rootaddr} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
|
||||
"updatekern=tftp ${loadaddr} ${kernelfile};" \
|
||||
" era ${kerneladdr} +${filesize};" \
|
||||
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
|
||||
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
|
||||
"boot_flash=run flashargs addtty addeth;" \
|
||||
" bootm ${kerneladdr}\0" \
|
||||
"boot_net=run netargs addtty addeth;" \
|
||||
" tftpboot ${loadaddr} ${kernelfile};" \
|
||||
" bootm\0"
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue