Add support for MPC8220 based "sorcery" board.

CHANGELOG

@@ -2,7 +2,9 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
-* Add support for TQM8560 board
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.
 
 * Add FEC support for TQM8540 board.
   Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC

Makefile

@@ -864,6 +864,9 @@ XPEDITE1K_config:	unconfig
 Alaska8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 alaska
 
+sorcery_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 sorcery
+
 Yukon8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 yukon
 

board/alaska/Makefile

@@ -1,4 +1,4 @@
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o extserial.o serial.o
+OBJS	:= $(BOARD).o flash.o extserial.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/sorcery/Makefile

@@ -0,0 +1,45 @@
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/sorcery/config.mk

@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# sorcery board
+#
+
+TEXT_BASE = 0xfff00000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/sorcery/sorcery.c

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004, Freescale Inc.
+ * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8220.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+long int initdram (int board_type)
+{
+	ulong size;
+
+	size = dramSetup ();
+	
+	return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sorcery-C MPC8220\n");
+
+	return 0;
+}

board/sorcery/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8220/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

cpu/mpc8220/Makefile

@@ -27,8 +27,9 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 ASOBJS	= io.o fec_dma_tasks.o
-OBJS	= i2c.o traps.o cpu.o cpu_init.o fec.o dramSetup.o interrupts.o \
+OBJS	= cpu.o cpu_init.o dramSetup.o fec.o i2c.o \
-	  loadtask.o uart.o speed.o
+	  interrupts.o loadtask.o serial.o speed.o \
+	  traps.o uart.o
 
 all:	.depend $(START) $(ASOBJS) $(LIB)
 

cpu/mpc8220/cpu_init.c

@@ -55,7 +55,11 @@ void cpu_init_f (void)
 	 */
 #if defined (CFG_CS0_BASE)
 	flexbus->csar0 = CFG_CS0_BASE;
+
+/* Sorcery-C can hang-up after CTRL reg initialization */
+#if defined (CFG_CS0_CTRL)
 	flexbus->cscr0 = CFG_CS0_CTRL;
+#endif
 	flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
 	__asm__ volatile ("sync");
 #endif
@@ -97,15 +101,15 @@ void cpu_init_f (void)
 	/* This section of the code cannot place in cpu_init_r(),
 	   it will cause the system to hang */
 	/* enable timebase */
-	xlbarb->config = 0x00002000;
-
 	xlbarb->addrTenTimeOut = 0x1000;
 	xlbarb->dataTenTimeOut = 0x1000;
 	xlbarb->busActTimeOut = 0x2000;
 
+	xlbarb->config = 0x00002000;
+
 	/* Master Priority Enable */
-	xlbarb->mastPriEn = 0x1f;
 	xlbarb->mastPriority = 0;
+	xlbarb->mastPriEn = 0x1f;
 }
 
 /*

cpu/mpc8220/dramSetup.c

@@ -32,9 +32,9 @@ characteristics to initialize the dram on MPC8220
 #include "i2cCore.h"
 #include "dramSetup.h"
 
-#define SPD_SIZE    0x40
+#define SPD_SIZE	CFG_SDRAM_SPD_SIZE
-#define DRAM_SPD    0xA2	/* on Board SPD eeprom */
+#define DRAM_SPD	(CFG_SDRAM_SPD_I2C_ADDR)<<1	/* on Board SPD eeprom */
-#define TOTAL_BANK  2
+#define TOTAL_BANK	CFG_SDRAM_TOTAL_BANKS
 
 int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
 {
@@ -144,7 +144,7 @@ int readSpdData (u8 * spdData)
 		break;
 	}
 
-	pi2cReg->adr = 0x90;	/* I2C device address */
+	pi2cReg->adr = CFG_I2C_SLAVE<<1;
 
 	pi2cReg->cr = I2C_CTL_EN;	/* Set Enable         */
 
@@ -569,7 +569,7 @@ u32 dramSetup (void)
 	cfg_value |= CFG1_SWT2RWP ((type == TYPE_DDR) ? 7 : 2);
 
 	/* Set the Read CAS latency.  We're going to use a CL of
-	 * 2 for DDR and SDR.
+	 * 2.5 for DDR and 2 SDR.
 	 */
 	cfg_value |= CFG1_RLATENCY ((type == TYPE_DDR) ? 7 : 2);
 
@@ -685,10 +685,14 @@ u32 dramSetup (void)
 	}
 
 
-	/* Set up mode value for CAS latency == 2 */
+	/* Set up mode value for CAS latency */
+#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
+	mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
+		MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
+#else
 	mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
 		      MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2) | MODE_CMD);
-
+#endif
 	asm volatile ("sync");
 
 	/* Write Extended Mode  - enable DLL */
@@ -698,7 +702,7 @@ u32 dramSetup (void)
 		memctl->mode = (temp >> 16);	/* mode */
 		asm volatile ("sync");
 
-		/* Write Mode - reset DLL, set CAS latency == 2 */
+		/* Write Mode - reset DLL, set CAS latency */
 		temp = mode_value | MODE_OPMODE (MODE_OPMODE_RESETDLL);
 		memctl->mode = (temp >> 16);	/* mode */
 		asm volatile ("sync");

cpu/mpc8220/speed.c

@@ -42,30 +42,30 @@ int get_clocks (void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 	pllcfg_t bus2core[] = {
-		{0x10, 2, 8},	/* 1 */
+		{0x02, 2, 8},	/* 1 */
-		{0x08, 2, 4},
+		{0x01, 2, 4},
-		{0x60, 3, 8},	/* 1.5 */
+		{0x0C, 3, 8},	/* 1.5 */
 		{0x00, 3, 4},
-		{0xc0, 3, 2},
+		{0x18, 3, 2},
-		{0x28, 4, 4},	/* 2 */
+		{0x05, 4, 4},	/* 2 */
-		{0x20, 4, 2},
+		{0x04, 4, 2},
-		{0x88, 5, 4},	/* 2.5 */
+		{0x11, 5, 4},	/* 2.5 */
-		{0x30, 5, 2},
+		{0x06, 5, 2},
-		{0x80, 6, 4},	/* 3 */
+		{0x10, 6, 4},	/* 3 */
-		{0x40, 6, 2},
+		{0x08, 6, 2},
-		{0x70, 7, 2},	/* 3.5 */
+		{0x0E, 7, 2},	/* 3.5 */
-		{0x50, 8, 2},	/* 4 */
+		{0x0A, 8, 2},	/* 4 */
-		{0x38, 9, 2},	/* 4.5 */
+		{0x07, 9, 2},	/* 4.5 */
-		{0x58, 10, 2},	/* 5 */
+		{0x0B, 10, 2},	/* 5 */
-		{0x48, 11, 2},	/* 5.5 */
+		{0x09, 11, 2},	/* 5.5 */
-		{0x68, 12, 2},	/* 6 */
+		{0x0D, 12, 2},	/* 6 */
-		{0x90, 13, 2},	/* 6.5 */
+		{0x12, 13, 2},	/* 6.5 */
-		{0xa0, 14, 2},	/* 7 */
+		{0x14, 14, 2},	/* 7 */
-		{0xb0, 15, 2},	/* 7.5 */
+		{0x16, 15, 2},	/* 7.5 */
-		{0xe0, 16, 2}	/* 8 */
+		{0x1C, 16, 2}	/* 8 */
 	};
 	u32 hid1;
-	int i, size;
+	int i, size, pci2bus;
 
 #if !defined(CFG_MPC8220_CLKIN)
 #error clock measuring not implemented yet - define CFG_MPC8220_CLKIN
@@ -73,9 +73,12 @@ int get_clocks (void)
 
 	gd->inp_clk = CFG_MPC8220_CLKIN;
 
-	/* Bus clock is fixed at 120Mhz for now */
+	/* Read XLB to PCI(INP) clock multiplier */
-	/* will do dynamic in the future */
+	pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & 
-	gd->bus_clk = CFG_MPC8220_CLKIN * 4;
+		PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;
+
+	/* XLB bus clock */
+	gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus;
 
 	/* PCI clock is same as input clock */
 	gd->pci_clk = CFG_MPC8220_CLKIN;
@@ -88,14 +91,13 @@ int get_clocks (void)
 	asm volatile ("mfspr %0, 1009":"=r" (hid1):);
 
 	size = sizeof (bus2core) / sizeof (pllcfg_t);
-	hid1 >>= 24;
+
+	hid1 >>= 27;
 
 	for (i = 0; i < size; i++)
 		if (hid1 == bus2core[i].hid1) {
 			gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-			/* Input Multiplier is determined by MPLL,
+			gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
-			   hardcoded for now at 16 */
-			gd->vco_clk = gd->pci_clk * 16;
 			break;
 		}
 

cpu/mpc8220/start.S

@@ -111,6 +111,7 @@ boot_warm:
 
 	/* MBAR is mirrored into the MBAR SPR */
 	mtspr	MBAR,r3
+	mtspr	SPRN_SPRG7W,r3	
 	lis	r4, CFG_DEFAULT_MBAR@h
 	stw	r3, 0(r4)
 #endif /* CFG_DEFAULT_MBAR */

cpu/mpc8220/uart.c

@@ -47,8 +47,7 @@ int psc_serial_init (void)
 	/* write to CSR: RX/TX baud rate from timers */
 	psc->sr_csr = 0xdd000000;
 
-	psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR1_RX_RTS;
+	psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; 
-	psc->mr1_2 = PSC_MR2_STOP_BITS_1 | PSC_MR2_TX_CTS;
 
 	/* Setting up BaudRate */
 	counter = ((gd->bus_clk / gd->baudrate)) >> 5;
@@ -77,7 +76,7 @@ void psc_serial_putc (const char c)
 		serial_putc ('\r');
 
 	/* Wait for last character to go. */
-	while (!(psc->sr_csr & PSC_SR_TXEMT));
+	while (!(psc->sr_csr & PSC_SR_TXRDY));
 
 	psc->xmitbuf[0] = c;
 }

include/configs/Alaska8220.h

@@ -34,6 +34,7 @@
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
 #define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	*/
@@ -258,6 +259,12 @@
 #define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
 #define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
+/* SDRAM configuration */
+#define CFG_SDRAM_TOTAL_BANKS           2
+#define CFG_SDRAM_SPD_I2C_ADDR          0x51            /* 7bit */
+#define CFG_SDRAM_SPD_SIZE              0x40
+#define CFG_SDRAM_CAS_LATENCY           4               /* (CL=2)x2 */
+
 /*
  * Ethernet configuration
  */

include/configs/sorcery.h

@@ -0,0 +1,277 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220		1
+#define CONFIG_SORCERY		1	/* Sorcery board */
+
+/* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
+   determine the CPU speed. */
+#define CFG_MPC8220_CLKIN	60000000 /* ... running at 60MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5   	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC */
+
+#define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BOOTD	| \
+				CFG_CMD_CACHE	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_SNTP	| \
+				0)
+
+/*			CFG_CMD_MII	| \ */
+/*			       CFG_CMD_PCI	| \ */
+/*			       CFG_CMD_USB	| \ */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Default Environment
+ */
+#define CONFIG_BOOTDELAY	5    /* autoboot after 5 seconds */
+#define CONFIG_HOSTNAME		sorcery
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip;"					\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/sorcery/uImage\0"				\
+	"kernel_addr=FFE00000\0"					\
+	"ramdisk_addr=FFB00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_NET_MULTI
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CFG_I2C_MODULE		1
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef	CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Flexbus Chipselect configuration
+ * Beware: Some CS# seem to be mandatory (if these CS# are not set, 
+ * board can hang-up in unpredictable place). 
+ * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
+ */
+
+/* Flash */
+#define CFG_CS0_BASE		0xf800
+#define CFG_CS0_MASK		0x08000000 /* 128 MB (two chips) */
+
+/* Workaround of hang-up after setting ctrl register for flash
+   After reset this register has value 0x003ffd80, which differs
+   from suggested only by the number of wait states. 
+#define CFG_CS0_CTRL		0x003f1580
+*/
+
+/* NVM */
+#define CFG_CS1_BASE		0xf100
+#define CFG_CS1_MASK		0x00080000  /* 512K */
+#define CFG_CS1_CTRL		0x003ffd40  /* 8bit port size? */
+
+/* Atlas2 + Gemini */
+/* This CS# is mandatory? */
+#define CFG_CS2_BASE		0xf10A
+#define CFG_CS2_MASK		0x00020000 /* 2x64K*/
+#define CFG_CS2_CTRL		0x003ffd00 /* 32bit port size? */
+
+/* CAN Controller */
+/* This CS# is mandatory? */
+#define CFG_CS3_BASE		0xf10C
+#define CFG_CS3_MASK		0x00010000 /* 64K */
+#define CFG_CS3_CTRL		0x003ffd40 /* 8Bit port size */
+
+/* Foreign interface */
+#define CFG_CS4_BASE		0xF10D
+#define CFG_CS4_MASK		0x00010000 /* 64K */
+#define CFG_CS4_CTRL		0x003ffd80 /* 16bit port size */
+
+/* CPLD? */
+/* This CS# is mandatory? */
+#define CFG_CS5_BASE		0xF108
+#define CFG_CS5_MASK		0x00010000
+#define CFG_CS5_CTRL		0x003ffd80 /* 16bit port size */
+
+#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
+#define CFG_FLASH_BASE		CFG_FLASH0_BASE
+
+#define CFG_MAX_FLASH_BANKS	2	/* max num of memory banks (actually 4? (at least 2)) */
+#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip (actually 256) */
+
+
+#define PHYS_AMD_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_BANKS_LIST 	{ CFG_FLASH_BASE,  \
+				CFG_FLASH_BASE+0x04000000 } /* two banks */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH0_BASE)
+#define CFG_ENV_SIZE		PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE		0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+
+/* SDRAM configuration (for SPD) */
+#define CFG_SDRAM_TOTAL_BANKS		1
+#define CFG_SDRAM_SPD_I2C_ADDR		0x50  		/* 7bit */
+#define CFG_SDRAM_SPD_SIZE		0x100
+#define CFG_SDRAM_CAS_LATENCY		5 		/* (CL=2.5)x2 */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC	1
+#define CONFIG_FEC_10MBIT	1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR		0x1F
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			    /* undef to save memory	*/
+#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	    /* max number of command args   */
+#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR		0x100000    /* default load address */
+
+#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT		0 
+#define CFG_HID0_FINAL		0 
+
+#endif /* __CONFIG_H */

include/mpc8220.h

@@ -258,6 +258,10 @@
 /* equates for tx FIFO last write frame pointer reg */
 #define PSC_TFLWFPTR(x)		(x&0x1ff)     /* last write frame pointer */
 
+/* PCI configuration (only for PLL determination)*/
+#define PCI_REG_PCIGSCR 	(MMAP_XCPCI + 0x60) /* Global status/control register */
+#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK	0x07000000
+#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT		24
 
 /* ------------------------------------------------------------------------ */
 /*
@@ -306,7 +310,7 @@
 #define CFG_CS2_PORT3_CONFIG	0x10000000
 #define CFG_CS3_PORT3_CONFIG	0x40000000
 #define CFG_CS4_PORT3_CONFIG	0x00000400
-#define CFG_CS5_PORT3_CONFIG	0x00000100
+#define CFG_CS5_PORT3_CONFIG	0x00000200
 #define CFG_I2C_PORT3_CONFIG	0x003c0000
 
 /* ------------------------------------------------------------------------ */