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Coding style cleanup

This commit is contained in:
Wolfgang Denk 2005-08-02 17:06:17 +02:00
parent 797638f9ff
commit 095b8a3798
13 changed files with 236 additions and 242 deletions
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32
board/funkwerk/vovpn-gw/vovpn-gw.c
View File

@ -208,22 +208,22 @@ void reset_phy (void)
} }
static unsigned long UPMATable[] = { static unsigned long UPMATable[] = {
0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, //Words 0 to 3 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, //Words 4 to 7 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 8 to 11 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, //Words 24 to 27 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 28 to 31 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, //Words 32 to 35 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 48 to 51 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 //Words 60 to 63 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
}; };
int board_early_init_f (void) int board_early_init_f (void)

2
board/pm520/flash.c
View File

@ -351,8 +351,6 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
return ret; return ret;
} }
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
*/ */

1
common/cmd_usb.c
View File

@ -457,7 +457,6 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* try to recognize storage devices immediately */ /* try to recognize storage devices immediately */
if (i >= 0) if (i >= 0)
usb_stor_curr_dev = usb_stor_scan(1); usb_stor_curr_dev = usb_stor_scan(1);
#endif #endif
return 0; return 0;
} }

1
common/usb.c
View File

@ -46,7 +46,6 @@
#include <405gp_pci.h> #include <405gp_pci.h>
#endif #endif
#undef USB_DEBUG #undef USB_DEBUG
#ifdef USB_DEBUG #ifdef USB_DEBUG

2
cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -1220,8 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
return stat; return stat;
} }
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */ /* common code for handling submit messages - used for all but root hub */

154
include/configs/bamboo.h
View File

@ -30,13 +30,13 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* High Level Configuration Options * High Level Configuration Options
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */ #define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */ #undef CFG_DRAM_TEST /* disable - takes long time! */
//#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ /*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
@ -64,24 +64,24 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM) * Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000 #define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ #define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
//#define CFG_SDRAM_BANKS (2) /*#define CFG_SDRAM_BANKS (2) */
#define CFG_SDRAM_BANKS (1) #define CFG_SDRAM_BANKS (1)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Serial Port * Serial Port
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1 #define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/ /*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE #undef CONFIG_UART1_CONSOLE
@ -95,8 +95,8 @@
* The DS1558 code assumes this condition * The DS1558 code assumes this condition
* *
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH related * FLASH related
@ -109,9 +109,9 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else #else
#define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
@ -125,7 +125,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* DDR SDRAM * DDR SDRAM
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C * I2C
@ -139,9 +139,9 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Environment * Environment
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_IS_IN_EEPROM 1
/* Define to allow the user to overwrite serial and ethaddr */ /* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE #define CONFIG_ENV_OVERWRITE
@ -158,12 +158,12 @@
#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */ #define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
#define CONFIG_BOOTDELAY 3 /* disable autoboot */ #define CONFIG_BOOTDELAY 3 /* disable autoboot */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3 #define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
@ -196,49 +196,49 @@
#ifdef CONFIG_440_EP #ifdef CONFIG_440_EP
/* Need to define POST */ /* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \ CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#else #else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#endif #endif
@ -263,8 +263,8 @@
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
@ -273,18 +273,18 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
/* General PCI */ /* General PCI */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */ /* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT #define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT #define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data

110
include/configs/walnut.h
View File

@ -34,21 +34,21 @@
*/ */
#define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ #define CONFIG_WALNUT 1 /* ...on a WALNUT board */
/* ...and on a SYCAMORE board */ /* ...and on a SYCAMORE board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_PREBOOT "echo;" \ #define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo" "echo"
#undef CONFIG_BOOTARGS #undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \ "netdev=eth0\0" \
"hostname=walnut\0" \ "hostname=walnut\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsargs=setenv bootargs root=/dev/nfs rw " \
@ -62,15 +62,15 @@
"bootm $(kernel_addr)\0" \ "bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip addtty;" \ "flash_self=run ramargs addip addtty;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \ "bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
"bootm\0" \ "bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/walnut/uImage\0" \ "bootfile=/tftpboot/walnut/uImage\0" \
"kernel_addr=fff80000\0" \ "kernel_addr=fff80000\0" \
"ramdisk_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \
"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \ "cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \ "setenv filesize;saveenv\0" \
"upd=run load;run update\0" \ "upd=run load;run update\0" \
"" ""
@ -88,7 +88,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
@ -105,7 +105,7 @@
CFG_CMD_NFS | \ CFG_CMD_NFS | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_SNTP ) CFG_CMD_SNTP )
@ -122,9 +122,9 @@
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
@ -143,9 +143,9 @@
* set Linux BASE_BAUD to 403200. * set Linux BASE_BAUD to 403200.
*/ */
#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200 #define CFG_BASE_BAUD 691200
/* The following table includes the supported baudrates */ /* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \ #define CFG_BAUDRATE_TABLE \
@ -154,10 +154,10 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@ -168,7 +168,7 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_SLAVE 0x7F
@ -176,24 +176,24 @@
* PCI stuff * PCI stuff
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */ #define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */ /* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Start addresses for the final memory configuration * Start addresses for the final memory configuration
@ -209,10 +209,10 @@
/* /*
* Define here the location of the environment variables (FLASH or NVRAM). * Define here the location of the environment variables (FLASH or NVRAM).
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
* supported for backward compatibility. * supported for backward compatibility.
*/ */
#if 1 #if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else #else
#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#endif #endif
@ -227,8 +227,8 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH organization * FLASH organization
*/ */
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
@ -238,14 +238,14 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ADDR0 0x5555 #define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa #define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char #define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH #ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */ /* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@ -280,44 +280,44 @@
/* Memory Bank 0 (Flash Bank 0) initialization */ /* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x9B015480 #define CFG_EBC_PB0AP 0x9B015480
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB1AP 0x02815480 #define CFG_EBC_PB1AP 0x02815480
#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB2AP 0x04815A80 #define CFG_EBC_PB2AP 0x04815A80
#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB3AP 0x01815280 #define CFG_EBC_PB3AP 0x01815280
#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB7AP 0x01815280 #define CFG_EBC_PB7AP 0x01815280
#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ #define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* External peripheral base address * External peripheral base address
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
#define CFG_KEY_REG_BASE_ADDR 0xF0100000 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
#define CFG_IR_REG_BASE_ADDR 0xF0200000 #define CFG_IR_REG_BASE_ADDR 0xF0200000
#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area * Definitions for initial stack pointer and data area
*/ */
#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ #define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ #define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address * Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings) * (to get SDRAM settings)
*/ */
#define SPD_EEPROM_ADDRESS 0x50 #define SPD_EEPROM_ADDRESS 0x50
/* /*
* Internal Definitions * Internal Definitions

62
include/configs/yellowstone.h
View File

@ -28,11 +28,11 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* High Level Configuration Options * High Level Configuration Options
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */ #define CONFIG_YELLOWSTONE 1 /* Board is BAMBOO */
#define CONFIG_440_GR 1 /* Specific PPC440GR support */ #define CONFIG_440_GR 1 /* Specific PPC440GR support */
#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */ #undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
@ -63,14 +63,14 @@
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000 #define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ #define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2) #define CFG_SDRAM_BANKS (2)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Serial Port * Serial Port
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
@ -92,7 +92,7 @@
* *
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH related * FLASH related
@ -107,7 +107,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* DDR SDRAM * DDR SDRAM
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C * I2C
@ -121,7 +121,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Environment * Environment
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_IS_IN_EEPROM 1
@ -144,7 +144,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3 #define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
@ -178,48 +178,48 @@
#ifdef CONFIG_440_EP #ifdef CONFIG_440_EP
/* Need to define POST */ /* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \ CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#else #else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#endif #endif
@ -246,7 +246,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
@ -255,18 +255,18 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
/* General PCI */ /* General PCI */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */ /* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT #define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT #define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data

68
include/configs/yosemite.h
View File

@ -28,11 +28,11 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* High Level Configuration Options * High Level Configuration Options
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is BAMBOO */ #define CONFIG_YOSEMITE 1 /* Board is BAMBOO */
#define CONFIG_440_EP 1 /* Specific PPC440EP support */ #define CONFIG_440_EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* disable - takes long time! */ #undef CFG_DRAM_TEST /* disable - takes long time! */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
@ -63,14 +63,14 @@
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */ #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
#define CFG_INIT_RAM_END 0x2000 #define CFG_INIT_RAM_END 0x2000
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */ #define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2) #define CFG_SDRAM_BANKS (2)
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Serial Port * Serial Port
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
@ -92,7 +92,7 @@
* *
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FLASH related * FLASH related
@ -105,9 +105,9 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
#else #else
#define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
@ -121,7 +121,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* DDR SDRAM * DDR SDRAM
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* I2C * I2C
@ -135,7 +135,7 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Environment * Environment
*----------------------------------------------------------------------*/ *----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/ #undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_IS_IN_EEPROM 1
@ -158,7 +158,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */ #define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3 #define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
@ -192,48 +192,48 @@
#ifdef CONFIG_440_EP #ifdef CONFIG_440_EP
/* Need to define POST */ /* Need to define POST */
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
CFG_CMD_USB | \ CFG_CMD_USB | \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#else #else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_DHCP | \ CFG_CMD_DHCP | \
CFG_CMD_DIAG | \ CFG_CMD_DIAG | \
CFG_CMD_ECHO | \ CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \ CFG_CMD_EEPROM | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
/* CFG_CMD_EXT2 |*/ \ /* CFG_CMD_EXT2 |*/ \
/* CFG_CMD_FAT |*/ \ /* CFG_CMD_FAT |*/ \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
/* CFG_CMD_IDE |*/ \ /* CFG_CMD_IDE |*/ \
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
/* CFG_CMD_KGDB |*/ \ /* CFG_CMD_KGDB |*/ \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_PCI | \ CFG_CMD_PCI | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO | \ CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \ CFG_CMD_SDRAM | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
/* CFG_CMD_SPI |*/ \ /* CFG_CMD_SPI |*/ \
0 ) & ~CFG_CMD_IMLS) 0 ) & ~CFG_CMD_IMLS)
#endif #endif
@ -260,7 +260,7 @@
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */ #define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
@ -269,18 +269,18 @@
*----------------------------------------------------------------------- *-----------------------------------------------------------------------
*/ */
/* General PCI */ /* General PCI */
#define CONFIG_PCI /* include pci support */ #define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */ /* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT #define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT #define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data