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rockchip: sdram: Use the rk_clr/setreg() interface 

Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2016-01-21 19:44:01 -07:00
parent a4b10c088c
commit 0906995bf3
1 changed files with 3 additions and 4 deletions
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7
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
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@ -400,7 +400,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
if (n == 1) {
setbits_le32(&pctl->ppcfg, 1);
writel(RK_SETBITS(1 << (8 + channel)), &grf->soc_con0);
rk_setreg(&grf->soc_con0, 1 << (8 + channel));
setbits_le32(&msch->ddrtiming, 1 << 31);
/* Data Byte disable*/
clrbits_le32(&publ->datx8[2].dxgcr, 1);
@ -410,7 +410,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
} else {
clrbits_le32(&pctl->ppcfg, 1);
writel(RK_CLRBITS(1 << (8 + channel)), &grf->soc_con0);
rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
clrbits_le32(&msch->ddrtiming, 1 << 31);
/* Data Byte enable*/
setbits_le32(&publ->datx8[2].dxgcr, 1);
@ -571,8 +571,7 @@ static void dram_all_config(const struct dram_info *dram,
dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
}
writel(sys_reg, &dram->pmu->sys_reg[2]);
writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride),
&dram->sgrf->soc_con2);
rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
}
static int sdram_init(const struct dram_info *dram,