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ppc4xx: Small whitespace fix of esd patches 

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-03-31 12:20:48 +02:00
parent 034394abb5
commit 02e3892021
3 changed files with 7 additions and 7 deletions
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10
board/esd/pmc440/cmd_pmc440.c
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@ -503,15 +503,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* map PCI address at 0xc0000000 in PLB space */ /* map PCI address at 0xc0000000 in PLB space */
/* PMM1 Mask/Attribute - disabled b4 setting */ /* PMM1 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1MA, 0x00000000); out32r(PCIX0_PMM1MA, 0x00000000);
/* PMM1 Local Address */ /* PMM1 Local Address */
out32r(PCIX0_PMM1LA, 0xc0000000); out32r(PCIX0_PMM1LA, 0xc0000000);
/* PMM1 PCI Low Address */ /* PMM1 PCI Low Address */
out32r(PCIX0_PMM1PCILA, pciaddr); out32r(PCIX0_PMM1PCILA, pciaddr);
/* PMM1 PCI High Address */ /* PMM1 PCI High Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); out32r(PCIX0_PMM1PCIHA, 0x00000000);
/* 256MB + No prefetching, and enable region */ /* 256MB + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0xf0000001); out32r(PCIX0_PMM1MA, 0xf0000001);
} else { } else {
printf("Usage:\npmm %s\n", cmdtp->help); printf("Usage:\npmm %s\n", cmdtp->help);

2
board/esd/pmc440/pmc440.c
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@ -565,7 +565,7 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID); CFG_PCI_SUBSYS_VENDORID);
/* disabled for PMC405 backward compatibility */ /* disabled for PMC405 backward compatibility */
/* Configure command register as bus master */ /* Configure command register as bus master */
/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */ /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */

2
include/configs/DU440.h
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@ -158,7 +158,7 @@
#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */ #define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
/* 440EPx errata CHIP 11 */ /* 440EPx errata CHIP 11 */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#define CONFIG_DDR_ECC /* Use ECC when available */ #define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50} #define SPD_EEPROM_ADDRESS {0x50}