tricorder: support 256MiB SDRAM on revision > D
Signed-off-by: Andreas Bießmann <andreas.biessmann@corscience.de>
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@ -154,12 +154,43 @@ int board_mmc_init(bd_t *bis)
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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/* General SDRC config */
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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struct tricorder_eeprom eeprom;
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get_eeprom(&eeprom);
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/* AC timings */
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->mr = MICRON_V_MR_165;
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/* General SDRC config */
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if (eeprom.board_version[0] > 'D') {
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/* use optimized timings for our SDRAM device */
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timings->mcfg = MCFG((256 << 20), 14);
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#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */
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/* 15/6 + 18/6 = 5.5 -> 6 */
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#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */
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#define MT46H64M32_TRRD 2 /* 12/6 = 2 */
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#define MT46H64M32_TRCD 3 /* 18/6 = 3 */
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#define MT46H64M32_TRP 3 /* 18/6 = 3 */
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#define MT46H64M32_TRAS 7 /* 42/6 = 7 */
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#define MT46H64M32_TRC 10 /* 60/6 = 10 */
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#define MT46H64M32_TRFC 12 /* 72/6 = 12 */
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timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC,
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MT46H64M32_TRAS, MT46H64M32_TRP,
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MT46H64M32_TRCD, MT46H64M32_TRRD,
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MT46H64M32_TDPL,
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MT46H64M32_TDAL);
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#define MT46H64M32_TWTR 1
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#define MT46H64M32_TCKE 1
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#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */
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#define MT46H64M32_TXP 1
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timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE,
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MT46H64M32_TXP, MT46H64M32_XSR);
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timings->mr = MICRON_V_MR_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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} else {
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/* use conservative beagleboard timings as default */
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timings->mcfg = MICRON_V_MCFG_165(128 << 20);
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timings->ctrla = MICRON_V_ACTIMA_165;
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timings->ctrlb = MICRON_V_ACTIMB_165;
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timings->mr = MICRON_V_MR_165;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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}
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}
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@ -354,7 +354,7 @@
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
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#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
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#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */
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#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
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#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
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