V3s_Allwinner
/
uboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 2 Wiki Activity
uboot/arch/x86/dts/serial.dtsi

10 lines
152 B
Plaintext
Raw Normal View History

x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
/ {
x86: Add support for Intel Minnowboard Max This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-28 05:13:47 +00:00
serial: serial {
ns16550: unify serial_x86 Unify serial_x86, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-19 13:48:06 +00:00
compatible = "ns16550";
x86: Clean up the board dts files This commits cleans up the board dts files. - Correct the serial port register size to 8 - Remove the misleading status = "disabled" statement in the serial.dtsi - Move the inclusion of skeleton.dtsi from serial.dtsi to board dts files - Let the board dts file define stdout-path in the chosen node - Remove device nodes in board dts files thar are duplicated to skeleton.dtsi Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-24 05:06:39 +00:00
reg = <0x3f8 8>;
dm: x86: dts: Add additional info to the serial port node Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-10 13:49:19 +00:00
reg-shift = <0>;
x86: Use ePAPR defined properties for x86-uart Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2014-12-31 08:05:13 +00:00
clock-frequency = <1843200>;
current-speed = <115200>;
x86: fdt: Create basic .dtsi file for coreboot This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-03 13:56:51 +00:00
};
};