46 lines
711 B
C
46 lines
711 B
C
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_CLOCK_H
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#define _ASM_ARCH_CLOCK_H
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/* define pll mode */
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#define RKCLK_PLL_MODE_SLOW 0
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#define RKCLK_PLL_MODE_NORMAL 1
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enum {
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ROCKCHIP_SYSCON_NOC,
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ROCKCHIP_SYSCON_GRF,
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ROCKCHIP_SYSCON_SGRF,
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ROCKCHIP_SYSCON_PMU,
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};
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/* Standard Rockchip clock numbers */
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enum rk_clk_id {
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CLK_OSC,
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CLK_ARM,
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CLK_DDR,
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CLK_CODEC,
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CLK_GENERAL,
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CLK_NEW,
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CLK_COUNT,
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};
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static inline int rk_pll_id(enum rk_clk_id clk_id)
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{
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return clk_id - 1;
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}
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/**
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* rockchip_get_cru() - get a pointer to the clock/reset unit registers
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*
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* @return pointer to registers, or -ve error on error
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*/
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void *rockchip_get_cru(void);
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#endif
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