153 lines
4.1 KiB
C
153 lines
4.1 KiB
C
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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extern void board_pll_init_f(void);
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/* Some specific Acadia Defines */
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#define CPLD_BASE 0x80000000
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void liveoak_gpio_init(void)
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{
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/*
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* GPIO0 setup (select GPIO or alternate function)
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*/
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out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
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out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
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out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
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out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
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out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
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out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
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out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
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/*
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* Ultra (405EZ) was nice enough to add another GPIO controller
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*/
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out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
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out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
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out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
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out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
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out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
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out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
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out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
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}
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#if 0 /* test-only: not called at all??? */
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void ext_bus_cntlr_init(void)
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{
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#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
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mtebc(pb4ap, EBC_PB4AP);
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mtebc(pb4cr, EBC_PB4CR);
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#endif
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}
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#endif
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int board_early_init_f(void)
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{
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unsigned int reg;
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#if 0 /* test-only */
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/*
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* If CRAM memory and SPI/NAND boot, and if the CRAM memory is
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* already initialized by the pre-loader then we can't reinitialize
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* CPR registers, GPIO registers and EBC registers as this will
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* have the effect of un-initializing CRAM.
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*/
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spr_reg = (volatile unsigned long) mfspr(SPRG7);
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if (spr_reg != LOAK_CRAM) { /* != CRAM */
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board_pll_init_f();
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liveoak_gpio_init();
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ext_bus_cntlr_init();
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mtebc(pb1ap, CFG_EBC_PB1AP);
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mtebc(pb1cr, CFG_EBC_PB1CR);
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mtebc(pb2ap, CFG_EBC_PB2AP);
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mtebc(pb2cr, CFG_EBC_PB2CR);
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}
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#else
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board_pll_init_f();
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liveoak_gpio_init();
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/* ext_bus_cntlr_init(); */
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#endif
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#if 0 /* test-only (orig) */
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/*
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* If we boot from NAND Flash, we are running in
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* RAM, so disable the EBC_CS0 so that it goes back
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* to the NOR Flash. It will be enabled later
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* for the NAND Flash on EBC_CS1
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*/
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mfsdr(sdrultra0, reg);
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mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
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#endif
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#if 0 /* test-only */
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/* configure for NAND */
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mfsdr(sdrultra0, reg);
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reg &= ~SDR_ULTRA0_CSN_MASK;
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reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
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mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
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#endif
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/* USB Host core needs this bit set */
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mfsdr(sdrultra1, reg);
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mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000010);
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mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
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mtdcr(uictr, 0x00000010); /* set int trigger levels */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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int misc_init_f(void)
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{
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/* Set EPLD to take PHY out of reset */
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out8(CPLD_BASE + 0x05, 0x00);
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udelay(100000);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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