317 lines
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317 lines
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<head>
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<title>Using the GNU Compiler Collection (GCC): PowerPC Function Attributes</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC): PowerPC Function Attributes">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="RL78-Function-Attributes.html#RL78-Function-Attributes" rel="next" title="RL78 Function Attributes">
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="PowerPC-Function-Attributes"></a>
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<div class="header">
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<p>
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Next: <a href="RL78-Function-Attributes.html#RL78-Function-Attributes" accesskey="n" rel="next">RL78 Function Attributes</a>, Previous: <a href="Nvidia-PTX-Function-Attributes.html#Nvidia-PTX-Function-Attributes" accesskey="p" rel="prev">Nvidia PTX Function Attributes</a>, Up: <a href="Function-Attributes.html#Function-Attributes" accesskey="u" rel="up">Function Attributes</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="PowerPC-Function-Attributes-1"></a>
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<h4 class="subsection">6.31.23 PowerPC Function Attributes</h4>
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<p>These function attributes are supported by the PowerPC back end:
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</p>
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<dl compact="compact">
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<dt><code>longcall</code></dt>
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<dt><code>shortcall</code></dt>
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<dd><a name="index-indirect-calls_002c-PowerPC"></a>
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<a name="index-longcall-function-attribute_002c-PowerPC"></a>
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<a name="index-shortcall-function-attribute_002c-PowerPC"></a>
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<p>The <code>longcall</code> attribute
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indicates that the function might be far away from the call site and
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require a different (more expensive) calling sequence. The
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<code>shortcall</code> attribute indicates that the function is always close
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enough for the shorter calling sequence to be used. These attributes
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override both the <samp>-mlongcall</samp> switch and
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the <code>#pragma longcall</code> setting.
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</p>
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<p>See <a href="RS_002f6000-and-PowerPC-Options.html#RS_002f6000-and-PowerPC-Options">RS/6000 and PowerPC Options</a>, for more information on whether long
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calls are necessary.
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</p>
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</dd>
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<dt><code>target (<var>options</var>)</code></dt>
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<dd><a name="index-target-function-attribute-3"></a>
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<p>As discussed in <a href="Common-Function-Attributes.html#Common-Function-Attributes">Common Function Attributes</a>, this attribute
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allows specification of target-specific compilation options.
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</p>
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<p>On the PowerPC, the following options are allowed:
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</p>
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<dl compact="compact">
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<dt>‘<samp>altivec</samp>’</dt>
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<dt>‘<samp>no-altivec</samp>’</dt>
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<dd><a name="index-target_0028_0022altivec_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) AltiVec instructions. In
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32-bit code, you cannot enable AltiVec instructions unless
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<samp>-mabi=altivec</samp> is used on the command line.
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</p>
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</dd>
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<dt>‘<samp>cmpb</samp>’</dt>
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<dt>‘<samp>no-cmpb</samp>’</dt>
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<dd><a name="index-target_0028_0022cmpb_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the compare bytes instruction
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implemented on the POWER6 processor and other processors that support
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the PowerPC V2.05 architecture.
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</p>
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</dd>
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<dt>‘<samp>dlmzb</samp>’</dt>
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<dt>‘<samp>no-dlmzb</samp>’</dt>
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<dd><a name="index-target_0028_0022dlmzb_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the string-search ‘<samp>dlmzb</samp>’
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instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
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generated by default when targeting those processors.
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</p>
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</dd>
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<dt>‘<samp>fprnd</samp>’</dt>
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<dt>‘<samp>no-fprnd</samp>’</dt>
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<dd><a name="index-target_0028_0022fprnd_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the FP round to integer
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instructions implemented on the POWER5+ processor and other processors
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that support the PowerPC V2.03 architecture.
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</p>
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</dd>
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<dt>‘<samp>hard-dfp</samp>’</dt>
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<dt>‘<samp>no-hard-dfp</samp>’</dt>
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<dd><a name="index-target_0028_0022hard_002ddfp_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the decimal floating-point
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instructions implemented on some POWER processors.
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</p>
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</dd>
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<dt>‘<samp>isel</samp>’</dt>
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<dt>‘<samp>no-isel</samp>’</dt>
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<dd><a name="index-target_0028_0022isel_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) ISEL instruction.
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</p>
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</dd>
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<dt>‘<samp>mfcrf</samp>’</dt>
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<dt>‘<samp>no-mfcrf</samp>’</dt>
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<dd><a name="index-target_0028_0022mfcrf_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the move from condition
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register field instruction implemented on the POWER4 processor and
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other processors that support the PowerPC V2.01 architecture.
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</p>
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</dd>
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<dt>‘<samp>mfpgpr</samp>’</dt>
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<dt>‘<samp>no-mfpgpr</samp>’</dt>
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<dd><a name="index-target_0028_0022mfpgpr_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the FP move to/from general
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purpose register instructions implemented on the POWER6X processor and
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other processors that support the extended PowerPC V2.05 architecture.
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</p>
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</dd>
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<dt>‘<samp>mulhw</samp>’</dt>
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<dt>‘<samp>no-mulhw</samp>’</dt>
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<dd><a name="index-target_0028_0022mulhw_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the half-word multiply and
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multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
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These instructions are generated by default when targeting those
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processors.
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</p>
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</dd>
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<dt>‘<samp>multiple</samp>’</dt>
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<dt>‘<samp>no-multiple</samp>’</dt>
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<dd><a name="index-target_0028_0022multiple_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the load multiple word
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instructions and the store multiple word instructions.
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</p>
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</dd>
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<dt>‘<samp>update</samp>’</dt>
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<dt>‘<samp>no-update</samp>’</dt>
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<dd><a name="index-target_0028_0022update_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the load or store instructions
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that update the base register to the address of the calculated memory
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location.
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</p>
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</dd>
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<dt>‘<samp>popcntb</samp>’</dt>
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<dt>‘<samp>no-popcntb</samp>’</dt>
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<dd><a name="index-target_0028_0022popcntb_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the popcount and double-precision
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FP reciprocal estimate instruction implemented on the POWER5
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processor and other processors that support the PowerPC V2.02
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architecture.
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</p>
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</dd>
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<dt>‘<samp>popcntd</samp>’</dt>
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<dt>‘<samp>no-popcntd</samp>’</dt>
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<dd><a name="index-target_0028_0022popcntd_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the popcount instruction
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implemented on the POWER7 processor and other processors that support
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the PowerPC V2.06 architecture.
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</p>
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</dd>
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<dt>‘<samp>powerpc-gfxopt</samp>’</dt>
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<dt>‘<samp>no-powerpc-gfxopt</samp>’</dt>
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<dd><a name="index-target_0028_0022powerpc_002dgfxopt_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the optional PowerPC
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architecture instructions in the Graphics group, including
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floating-point select.
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</p>
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</dd>
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<dt>‘<samp>powerpc-gpopt</samp>’</dt>
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<dt>‘<samp>no-powerpc-gpopt</samp>’</dt>
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<dd><a name="index-target_0028_0022powerpc_002dgpopt_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the optional PowerPC
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architecture instructions in the General Purpose group, including
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floating-point square root.
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</p>
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</dd>
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<dt>‘<samp>recip-precision</samp>’</dt>
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<dt>‘<samp>no-recip-precision</samp>’</dt>
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<dd><a name="index-target_0028_0022recip_002dprecision_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Assume (do not assume) that the reciprocal estimate instructions
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provide higher-precision estimates than is mandated by the PowerPC
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ABI.
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</p>
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</dd>
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<dt>‘<samp>string</samp>’</dt>
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<dt>‘<samp>no-string</samp>’</dt>
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<dd><a name="index-target_0028_0022string_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the load string instructions
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and the store string word instructions to save multiple registers and
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do small block moves.
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</p>
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</dd>
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<dt>‘<samp>vsx</samp>’</dt>
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<dt>‘<samp>no-vsx</samp>’</dt>
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<dd><a name="index-target_0028_0022vsx_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) vector/scalar (VSX)
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instructions, and also enable the use of built-in functions that allow
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more direct access to the VSX instruction set. In 32-bit code, you
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cannot enable VSX or AltiVec instructions unless
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<samp>-mabi=altivec</samp> is used on the command line.
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</p>
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</dd>
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<dt>‘<samp>friz</samp>’</dt>
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<dt>‘<samp>no-friz</samp>’</dt>
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<dd><a name="index-target_0028_0022friz_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate (do not generate) the <code>friz</code> instruction when the
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<samp>-funsafe-math-optimizations</samp> option is used to optimize
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rounding a floating-point value to 64-bit integer and back to floating
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point. The <code>friz</code> instruction does not return the same value if
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the floating-point number is too large to fit in an integer.
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</p>
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</dd>
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<dt>‘<samp>avoid-indexed-addresses</samp>’</dt>
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<dt>‘<samp>no-avoid-indexed-addresses</samp>’</dt>
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<dd><a name="index-target_0028_0022avoid_002dindexed_002daddresses_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that tries to avoid (not avoid) the use of indexed load
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or store instructions.
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</p>
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</dd>
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<dt>‘<samp>paired</samp>’</dt>
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<dt>‘<samp>no-paired</samp>’</dt>
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<dd><a name="index-target_0028_0022paired_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that uses (does not use) the generation of PAIRED simd
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instructions.
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</p>
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</dd>
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<dt>‘<samp>longcall</samp>’</dt>
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<dt>‘<samp>no-longcall</samp>’</dt>
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<dd><a name="index-target_0028_0022longcall_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Generate code that assumes (does not assume) that all calls are far
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away so that a longer more expensive calling sequence is required.
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</p>
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</dd>
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<dt>‘<samp>cpu=<var>CPU</var></samp>’</dt>
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<dd><a name="index-target_0028_0022cpu_003dCPU_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Specify the architecture to generate code for when compiling the
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function. If you select the <code>target("cpu=power7")</code> attribute when
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generating 32-bit code, VSX and AltiVec instructions are not generated
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unless you use the <samp>-mabi=altivec</samp> option on the command line.
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</p>
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</dd>
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<dt>‘<samp>tune=<var>TUNE</var></samp>’</dt>
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<dd><a name="index-target_0028_0022tune_003dTUNE_0022_0029-function-attribute_002c-PowerPC"></a>
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<p>Specify the architecture to tune for when compiling the function. If
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you do not specify the <code>target("tune=<var>TUNE</var>")</code> attribute and
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you do specify the <code>target("cpu=<var>CPU</var>")</code> attribute,
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compilation tunes for the <var>CPU</var> architecture, and not the
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default tuning specified on the command line.
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</p></dd>
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</dl>
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<p>On the PowerPC, the inliner does not inline a
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function that has different target options than the caller, unless the
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callee has a subset of the target options of the caller.
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</p></dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="RL78-Function-Attributes.html#RL78-Function-Attributes" accesskey="n" rel="next">RL78 Function Attributes</a>, Previous: <a href="Nvidia-PTX-Function-Attributes.html#Nvidia-PTX-Function-Attributes" accesskey="p" rel="prev">Nvidia PTX Function Attributes</a>, Up: <a href="Function-Attributes.html#Function-Attributes" accesskey="u" rel="up">Function Attributes</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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