366 lines
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366 lines
17 KiB
HTML
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<head>
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<title>Using the GNU Compiler Collection (GCC): AArch64 Options</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC): AArch64 Options">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" rel="next" title="Adapteva Epiphany Options">
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<link href="Submodel-Options.html#Submodel-Options" rel="prev" title="Submodel Options">
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<a name="AArch64-Options"></a>
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<div class="header">
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<p>
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Next: <a href="Adapteva-Epiphany-Options.html#Adapteva-Epiphany-Options" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="AArch64-Options-1"></a>
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<h4 class="subsection">3.18.1 AArch64 Options</h4>
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<a name="index-AArch64-Options"></a>
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<p>These options are defined for AArch64 implementations:
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</p>
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<dl compact="compact">
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<dt><code>-mabi=<var>name</var></code></dt>
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<dd><a name="index-mabi"></a>
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<p>Generate code for the specified data model. Permissible values
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are ‘<samp>ilp32</samp>’ for SysV-like data model where int, long int and pointers
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are 32 bits, and ‘<samp>lp64</samp>’ for SysV-like data model where int is 32 bits,
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but long int and pointers are 64 bits.
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</p>
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<p>The default depends on the specific target configuration. Note that
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the LP64 and ILP32 ABIs are not link-compatible; you must compile your
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entire program with the same ABI, and link with a compatible set of libraries.
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</p>
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</dd>
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<dt><code>-mbig-endian</code></dt>
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<dd><a name="index-mbig_002dendian"></a>
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<p>Generate big-endian code. This is the default when GCC is configured for an
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‘<samp>aarch64_be-*-*</samp>’ target.
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</p>
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</dd>
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<dt><code>-mgeneral-regs-only</code></dt>
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<dd><a name="index-mgeneral_002dregs_002donly"></a>
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<p>Generate code which uses only the general-purpose registers. This will prevent
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the compiler from using floating-point and Advanced SIMD registers but will not
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impose any restrictions on the assembler.
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</p>
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</dd>
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<dt><code>-mlittle-endian</code></dt>
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<dd><a name="index-mlittle_002dendian"></a>
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<p>Generate little-endian code. This is the default when GCC is configured for an
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‘<samp>aarch64-*-*</samp>’ but not an ‘<samp>aarch64_be-*-*</samp>’ target.
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</p>
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</dd>
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<dt><code>-mcmodel=tiny</code></dt>
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<dd><a name="index-mcmodel_003dtiny"></a>
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<p>Generate code for the tiny code model. The program and its statically defined
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symbols must be within 1MB of each other. Programs can be statically or
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dynamically linked.
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</p>
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</dd>
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<dt><code>-mcmodel=small</code></dt>
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<dd><a name="index-mcmodel_003dsmall"></a>
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<p>Generate code for the small code model. The program and its statically defined
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symbols must be within 4GB of each other. Programs can be statically or
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dynamically linked. This is the default code model.
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</p>
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</dd>
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<dt><code>-mcmodel=large</code></dt>
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<dd><a name="index-mcmodel_003dlarge"></a>
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<p>Generate code for the large code model. This makes no assumptions about
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addresses and sizes of sections. Programs can be statically linked only.
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</p>
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</dd>
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<dt><code>-mstrict-align</code></dt>
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<dd><a name="index-mstrict_002dalign"></a>
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<p>Avoid generating memory accesses that may not be aligned on a natural object
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boundary as described in the architecture specification.
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</p>
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</dd>
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<dt><code>-momit-leaf-frame-pointer</code></dt>
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<dt><code>-mno-omit-leaf-frame-pointer</code></dt>
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<dd><a name="index-momit_002dleaf_002dframe_002dpointer"></a>
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<a name="index-mno_002domit_002dleaf_002dframe_002dpointer"></a>
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<p>Omit or keep the frame pointer in leaf functions. The former behavior is the
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default.
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</p>
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</dd>
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<dt><code>-mtls-dialect=desc</code></dt>
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<dd><a name="index-mtls_002ddialect_003ddesc"></a>
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<p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
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of TLS variables. This is the default.
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</p>
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</dd>
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<dt><code>-mtls-dialect=traditional</code></dt>
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<dd><a name="index-mtls_002ddialect_003dtraditional"></a>
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<p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses
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of TLS variables.
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</p>
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</dd>
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<dt><code>-mtls-size=<var>size</var></code></dt>
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<dd><a name="index-mtls_002dsize"></a>
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<p>Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
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This option requires binutils 2.26 or newer.
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</p>
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</dd>
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<dt><code>-mfix-cortex-a53-835769</code></dt>
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<dt><code>-mno-fix-cortex-a53-835769</code></dt>
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<dd><a name="index-mfix_002dcortex_002da53_002d835769"></a>
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<a name="index-mno_002dfix_002dcortex_002da53_002d835769"></a>
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<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
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This involves inserting a NOP instruction between memory instructions and
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64-bit integer multiply-accumulate instructions.
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</p>
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</dd>
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<dt><code>-mfix-cortex-a53-843419</code></dt>
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<dt><code>-mno-fix-cortex-a53-843419</code></dt>
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<dd><a name="index-mfix_002dcortex_002da53_002d843419"></a>
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<a name="index-mno_002dfix_002dcortex_002da53_002d843419"></a>
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<p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
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This erratum workaround is made at link time and this will only pass the
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corresponding flag to the linker.
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</p>
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</dd>
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<dt><code>-mlow-precision-recip-sqrt</code></dt>
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<dt><code>-mno-low-precision-recip-sqrt</code></dt>
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<dd><a name="index-mlow_002dprecision_002drecip_002dsqrt"></a>
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<a name="index-mno_002dlow_002dprecision_002drecip_002dsqrt"></a>
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<p>Enable or disable the reciprocal square root approximation.
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This option only has an effect if <samp>-ffast-math</samp> or
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<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces
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precision of reciprocal square root results to about 16 bits for
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single precision and to 32 bits for double precision.
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</p>
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</dd>
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<dt><code>-mlow-precision-sqrt</code></dt>
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<dt><code>-mno-low-precision-sqrt</code></dt>
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<dd><a name="index-_002dmlow_002dprecision_002dsqrt"></a>
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<a name="index-_002dmno_002dlow_002dprecision_002dsqrt"></a>
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<p>Enable or disable the square root approximation.
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This option only has an effect if <samp>-ffast-math</samp> or
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<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces
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precision of square root results to about 16 bits for
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single precision and to 32 bits for double precision.
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If enabled, it implies <samp>-mlow-precision-recip-sqrt</samp>.
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</p>
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</dd>
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<dt><code>-mlow-precision-div</code></dt>
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<dt><code>-mno-low-precision-div</code></dt>
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<dd><a name="index-_002dmlow_002dprecision_002ddiv"></a>
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<a name="index-_002dmno_002dlow_002dprecision_002ddiv"></a>
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<p>Enable or disable the division approximation.
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This option only has an effect if <samp>-ffast-math</samp> or
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<samp>-funsafe-math-optimizations</samp> is used as well. Enabling this reduces
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precision of division results to about 16 bits for
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single precision and to 32 bits for double precision.
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</p>
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</dd>
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<dt><code>-march=<var>name</var></code></dt>
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<dd><a name="index-march"></a>
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<p>Specify the name of the target architecture and, optionally, one or
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more feature modifiers. This option has the form
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<samp>-march=<var>arch</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>.
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</p>
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<p>The permissible values for <var>arch</var> are ‘<samp>armv8-a</samp>’,
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‘<samp>armv8.1-a</samp>’, ‘<samp>armv8.2-a</samp>’ or <var>native</var>.
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</p>
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<p>The value ‘<samp>armv8.2-a</samp>’ implies ‘<samp>armv8.1-a</samp>’ and enables compiler
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support for the ARMv8.2-A architecture extensions.
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</p>
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<p>The value ‘<samp>armv8.1-a</samp>’ implies ‘<samp>armv8-a</samp>’ and enables compiler
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support for the ARMv8.1-A architecture extension. In particular, it
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enables the ‘<samp>+crc</samp>’ and ‘<samp>+lse</samp>’ features.
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</p>
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<p>The value ‘<samp>native</samp>’ is available on native AArch64 GNU/Linux and
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causes the compiler to pick the architecture of the host system. This
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option has no effect if the compiler is unable to recognize the
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architecture of the host system,
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</p>
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<p>The permissible values for <var>feature</var> are listed in the sub-section
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on <a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>
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Feature Modifiers</a>. Where conflicting feature modifiers are
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specified, the right-most feature is used.
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</p>
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<p>GCC uses <var>name</var> to determine what kind of instructions it can emit
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when generating assembly code. If <samp>-march</samp> is specified
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without either of <samp>-mtune</samp> or <samp>-mcpu</samp> also being
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specified, the code is tuned to perform well across a range of target
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processors implementing the target architecture.
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</p>
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</dd>
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<dt><code>-mtune=<var>name</var></code></dt>
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<dd><a name="index-mtune"></a>
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<p>Specify the name of the target processor for which GCC should tune the
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performance of the code. Permissible values for this option are:
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‘<samp>generic</samp>’, ‘<samp>cortex-a35</samp>’, ‘<samp>cortex-a53</samp>’, ‘<samp>cortex-a57</samp>’,
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‘<samp>cortex-a72</samp>’, ‘<samp>cortex-a73</samp>’, ‘<samp>exynos-m1</samp>’, ‘<samp>qdf24xx</samp>’,
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‘<samp>thunderx</samp>’, ‘<samp>xgene1</samp>’, ‘<samp>vulcan</samp>’, ‘<samp>cortex-a57.cortex-a53</samp>’,
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‘<samp>cortex-a72.cortex-a53</samp>’, ‘<samp>cortex-a73.cortex-a35</samp>’,
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‘<samp>cortex-a73.cortex-a53</samp>’, ‘<samp>native</samp>’.
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</p>
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<p>The values ‘<samp>cortex-a57.cortex-a53</samp>’, ‘<samp>cortex-a72.cortex-a53</samp>’,
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‘<samp>cortex-a73.cortex-a35</samp>’, ‘<samp>cortex-a73.cortex-a53</samp>’
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specify that GCC should tune for a big.LITTLE system.
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</p>
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<p>Additionally on native AArch64 GNU/Linux systems the value
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‘<samp>native</samp>’ tunes performance to the host system. This option has no effect
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if the compiler is unable to recognize the processor of the host system.
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</p>
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<p>Where none of <samp>-mtune=</samp>, <samp>-mcpu=</samp> or <samp>-march=</samp>
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are specified, the code is tuned to perform well across a range
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of target processors.
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</p>
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<p>This option cannot be suffixed by feature modifiers.
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</p>
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</dd>
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<dt><code>-mcpu=<var>name</var></code></dt>
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<dd><a name="index-mcpu"></a>
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<p>Specify the name of the target processor, optionally suffixed by one
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or more feature modifiers. This option has the form
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<samp>-mcpu=<var>cpu</var><span class="roman">{</span>+<span class="roman">[</span>no<span class="roman">]</span><var>feature</var><span class="roman">}*</span></samp>, where
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the permissible values for <var>cpu</var> are the same as those available
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for <samp>-mtune</samp>. The permissible values for <var>feature</var> are
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documented in the sub-section on
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<a href="#aarch64_002dfeature_002dmodifiers"><samp>-march</samp> and <samp>-mcpu</samp>
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Feature Modifiers</a>. Where conflicting feature modifiers are
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specified, the right-most feature is used.
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</p>
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<p>GCC uses <var>name</var> to determine what kind of instructions it can emit when
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generating assembly code (as if by <samp>-march</samp>) and to determine
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the target processor for which to tune for performance (as if
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by <samp>-mtune</samp>). Where this option is used in conjunction
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with <samp>-march</samp> or <samp>-mtune</samp>, those options take precedence
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over the appropriate part of this option.
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</p>
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</dd>
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<dt><code>-moverride=<var>string</var></code></dt>
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<dd><a name="index-moverride"></a>
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<p>Override tuning decisions made by the back-end in response to a
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<samp>-mtune=</samp> switch. The syntax, semantics, and accepted values
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for <var>string</var> in this option are not guaranteed to be consistent
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across releases.
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</p>
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<p>This option is only intended to be useful when developing GCC.
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</p>
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</dd>
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<dt><code>-mpc-relative-literal-loads</code></dt>
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<dd><a name="index-mpc_002drelative_002dliteral_002dloads"></a>
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<p>Enable PC-relative literal loads. With this option literal pools are
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accessed using a single instruction and emitted after each function. This
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limits the maximum size of functions to 1MB. This is enabled by default for
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<samp>-mcmodel=tiny</samp>.
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</p>
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</dd>
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</dl>
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<a name="g_t_002dmarch-and-_002dmcpu-Feature-Modifiers"></a>
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<h4 class="subsubsection">3.18.1.1 <samp>-march</samp> and <samp>-mcpu</samp> Feature Modifiers</h4>
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<a name="aarch64_002dfeature_002dmodifiers"></a><a name="index-_002dmarch-feature-modifiers"></a>
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<a name="index-_002dmcpu-feature-modifiers"></a>
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<p>Feature modifiers used with <samp>-march</samp> and <samp>-mcpu</samp> can be any of
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the following and their inverses <samp>no<var>feature</var></samp>:
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</p>
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<dl compact="compact">
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<dt>‘<samp>crc</samp>’</dt>
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<dd><p>Enable CRC extension. This is on by default for
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<samp>-march=armv8.1-a</samp>.
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</p></dd>
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<dt>‘<samp>crypto</samp>’</dt>
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<dd><p>Enable Crypto extension. This also enables Advanced SIMD and floating-point
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instructions.
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</p></dd>
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<dt>‘<samp>fp</samp>’</dt>
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<dd><p>Enable floating-point instructions. This is on by default for all possible
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values for options <samp>-march</samp> and <samp>-mcpu</samp>.
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</p></dd>
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<dt>‘<samp>simd</samp>’</dt>
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<dd><p>Enable Advanced SIMD instructions. This also enables floating-point
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instructions. This is on by default for all possible values for options
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<samp>-march</samp> and <samp>-mcpu</samp>.
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</p></dd>
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<dt>‘<samp>lse</samp>’</dt>
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<dd><p>Enable Large System Extension instructions. This is on by default for
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<samp>-march=armv8.1-a</samp>.
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</p></dd>
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<dt>‘<samp>fp16</samp>’</dt>
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<dd><p>Enable FP16 extension. This also enables floating-point instructions.
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</p>
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</dd>
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</dl>
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<p>Feature <samp>crypto</samp> implies <samp>simd</samp>, which implies <samp>fp</samp>.
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Conversely, <samp>nofp</samp> implies <samp>nosimd</samp>, which implies
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<samp>nocrypto</samp>.
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