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<a name="i860-Machine-Directives"></a>
<h4 class="subsection">9.16.3 i860 Machine Directives</h4>
<a name="index-machine-directives_002c-i860"></a>
<a name="index-i860-machine-directives"></a>
<dl compact="compact">
<dd><a name="index-dual-directive_002c-i860"></a>
</dd>
<dt><code>.dual</code></dt>
<dd><p>Enter dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the <code>d.</code> prefix.
</p></dd>
</dl>
<dl compact="compact">
<dd><a name="index-enddual-directive_002c-i860"></a>
</dd>
<dt><code>.enddual</code></dt>
<dd><p>Exit dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the <code>d.</code> prefix.
</p></dd>
</dl>
<dl compact="compact">
<dd><a name="index-atmp-directive_002c-i860"></a>
</dd>
<dt><code>.atmp</code></dt>
<dd><p>Change the temporary register used when expanding pseudo operations. The
default register is <code>r31</code>.
</p></dd>
</dl>
<p>The <code>.dual</code>, <code>.enddual</code>, and <code>.atmp</code> directives are available only in the Intel syntax mode.
</p>
<p>Both syntaxes allow for the standard <code>.align</code> directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: &quot;<code>.align type</code>&quot;, where &lsquo;type&rsquo; is one of <code>.short</code>, <code>.long</code>,
<code>.quad</code>, <code>.single</code>, <code>.double</code> representing alignments of 2, 4,
16, 4, and 8, respectively.
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