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434 lines
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<title>GNU Compiler Collection (GCC) Internals: Simple Constraints</title>
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Constraints.html#Constraints" rel="up" title="Constraints">
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<a name="Simple-Constraints"></a>
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<div class="header">
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<p>
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Next: <a href="Multi_002dAlternative.html#Multi_002dAlternative" accesskey="n" rel="next">Multi-Alternative</a>, Up: <a href="Constraints.html#Constraints" accesskey="u" rel="up">Constraints</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Simple-Constraints-1"></a>
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<h4 class="subsection">16.8.1 Simple Constraints</h4>
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<a name="index-simple-constraints"></a>
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<p>The simplest kind of constraint is a string full of letters, each of
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which describes one kind of operand that is permitted. Here are
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the letters that are allowed:
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</p>
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<dl compact="compact">
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<dt>whitespace</dt>
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<dd><p>Whitespace characters are ignored and can be inserted at any position
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except the first. This enables each alternative for different operands to
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be visually aligned in the machine description even if they have different
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number of constraints and modifiers.
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</p>
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<a name="index-m-in-constraint"></a>
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<a name="index-memory-references-in-constraints"></a>
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</dd>
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<dt>‘<samp>m</samp>’</dt>
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<dd><p>A memory operand is allowed, with any kind of address that the machine
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supports in general.
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Note that the letter used for the general memory constraint can be
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re-defined by a back end using the <code>TARGET_MEM_CONSTRAINT</code> macro.
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</p>
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<a name="index-offsettable-address"></a>
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<a name="index-o-in-constraint"></a>
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</dd>
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<dt>‘<samp>o</samp>’</dt>
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<dd><p>A memory operand is allowed, but only if the address is
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<em>offsettable</em>. This means that adding a small integer (actually,
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the width in bytes of the operand, as determined by its machine mode)
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may be added to the address and the result is also a valid memory
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address.
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</p>
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<a name="index-autoincrement_002fdecrement-addressing"></a>
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<p>For example, an address which is constant is offsettable; so is an
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address that is the sum of a register and a constant (as long as a
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slightly larger constant is also within the range of address-offsets
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supported by the machine); but an autoincrement or autodecrement
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address is not offsettable. More complicated indirect/indexed
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addresses may or may not be offsettable depending on the other
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addressing modes that the machine supports.
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</p>
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<p>Note that in an output operand which can be matched by another
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operand, the constraint letter ‘<samp>o</samp>’ is valid only when accompanied
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by both ‘<samp><</samp>’ (if the target machine has predecrement addressing)
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and ‘<samp>></samp>’ (if the target machine has preincrement addressing).
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</p>
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<a name="index-V-in-constraint"></a>
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</dd>
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<dt>‘<samp>V</samp>’</dt>
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<dd><p>A memory operand that is not offsettable. In other words, anything that
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would fit the ‘<samp>m</samp>’ constraint but not the ‘<samp>o</samp>’ constraint.
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</p>
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<a name="index-_003c-in-constraint"></a>
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</dd>
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<dt>‘<samp><</samp>’</dt>
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<dd><p>A memory operand with autodecrement addressing (either predecrement or
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postdecrement) is allowed. In inline <code>asm</code> this constraint is only
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allowed if the operand is used exactly once in an instruction that can
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handle the side-effects. Not using an operand with ‘<samp><</samp>’ in constraint
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string in the inline <code>asm</code> pattern at all or using it in multiple
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instructions isn’t valid, because the side-effects wouldn’t be performed
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or would be performed more than once. Furthermore, on some targets
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the operand with ‘<samp><</samp>’ in constraint string must be accompanied by
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special instruction suffixes like <code>%U0</code> instruction suffix on PowerPC
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or <code>%P0</code> on IA-64.
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</p>
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<a name="index-_003e-in-constraint"></a>
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</dd>
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<dt>‘<samp>></samp>’</dt>
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<dd><p>A memory operand with autoincrement addressing (either preincrement or
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postincrement) is allowed. In inline <code>asm</code> the same restrictions
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as for ‘<samp><</samp>’ apply.
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</p>
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<a name="index-r-in-constraint"></a>
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<a name="index-registers-in-constraints"></a>
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</dd>
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<dt>‘<samp>r</samp>’</dt>
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<dd><p>A register operand is allowed provided that it is in a general
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register.
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</p>
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<a name="index-constants-in-constraints"></a>
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<a name="index-i-in-constraint"></a>
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</dd>
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<dt>‘<samp>i</samp>’</dt>
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<dd><p>An immediate integer operand (one with constant value) is allowed.
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This includes symbolic constants whose values will be known only at
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assembly time or later.
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</p>
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<a name="index-n-in-constraint"></a>
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</dd>
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<dt>‘<samp>n</samp>’</dt>
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<dd><p>An immediate integer operand with a known numeric value is allowed.
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Many systems cannot support assembly-time constants for operands less
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than a word wide. Constraints for these operands should use ‘<samp>n</samp>’
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rather than ‘<samp>i</samp>’.
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</p>
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<a name="index-I-in-constraint"></a>
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</dd>
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<dt>‘<samp>I</samp>’, ‘<samp>J</samp>’, ‘<samp>K</samp>’, … ‘<samp>P</samp>’</dt>
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<dd><p>Other letters in the range ‘<samp>I</samp>’ through ‘<samp>P</samp>’ may be defined in
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a machine-dependent fashion to permit immediate integer operands with
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explicit integer values in specified ranges. For example, on the
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68000, ‘<samp>I</samp>’ is defined to stand for the range of values 1 to 8.
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This is the range permitted as a shift count in the shift
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instructions.
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</p>
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<a name="index-E-in-constraint"></a>
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</dd>
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<dt>‘<samp>E</samp>’</dt>
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<dd><p>An immediate floating operand (expression code <code>const_double</code>) is
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allowed, but only if the target floating point format is the same as
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that of the host machine (on which the compiler is running).
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</p>
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<a name="index-F-in-constraint"></a>
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</dd>
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<dt>‘<samp>F</samp>’</dt>
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<dd><p>An immediate floating operand (expression code <code>const_double</code> or
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<code>const_vector</code>) is allowed.
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</p>
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<a name="index-G-in-constraint"></a>
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<a name="index-H-in-constraint"></a>
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</dd>
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<dt>‘<samp>G</samp>’, ‘<samp>H</samp>’</dt>
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<dd><p>‘<samp>G</samp>’ and ‘<samp>H</samp>’ may be defined in a machine-dependent fashion to
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permit immediate floating operands in particular ranges of values.
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</p>
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<a name="index-s-in-constraint"></a>
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</dd>
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<dt>‘<samp>s</samp>’</dt>
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<dd><p>An immediate integer operand whose value is not an explicit integer is
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allowed.
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</p>
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<p>This might appear strange; if an insn allows a constant operand with a
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value not known at compile time, it certainly must allow any known
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value. So why use ‘<samp>s</samp>’ instead of ‘<samp>i</samp>’? Sometimes it allows
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better code to be generated.
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</p>
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<p>For example, on the 68000 in a fullword instruction it is possible to
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use an immediate operand; but if the immediate value is between -128
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and 127, better code results from loading the value into a register and
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using the register. This is because the load into the register can be
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done with a ‘<samp>moveq</samp>’ instruction. We arrange for this to happen
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by defining the letter ‘<samp>K</samp>’ to mean “any integer outside the
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range -128 to 127”, and then specifying ‘<samp>Ks</samp>’ in the operand
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constraints.
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</p>
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<a name="index-g-in-constraint"></a>
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</dd>
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<dt>‘<samp>g</samp>’</dt>
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<dd><p>Any register, memory or immediate integer operand is allowed, except for
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registers that are not general registers.
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</p>
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<a name="index-X-in-constraint"></a>
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</dd>
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<dt>‘<samp>X</samp>’</dt>
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<dd><p>Any operand whatsoever is allowed, even if it does not satisfy
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<code>general_operand</code>. This is normally used in the constraint of
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a <code>match_scratch</code> when certain alternatives will not actually
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require a scratch register.
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</p>
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<a name="index-0-in-constraint"></a>
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<a name="index-digits-in-constraint"></a>
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</dd>
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<dt>‘<samp>0</samp>’, ‘<samp>1</samp>’, ‘<samp>2</samp>’, … ‘<samp>9</samp>’</dt>
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<dd><p>An operand that matches the specified operand number is allowed. If a
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digit is used together with letters within the same alternative, the
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digit should come last.
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</p>
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<p>This number is allowed to be more than a single digit. If multiple
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digits are encountered consecutively, they are interpreted as a single
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decimal integer. There is scant chance for ambiguity, since to-date
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it has never been desirable that ‘<samp>10</samp>’ be interpreted as matching
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either operand 1 <em>or</em> operand 0. Should this be desired, one
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can use multiple alternatives instead.
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</p>
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<a name="index-matching-constraint"></a>
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<a name="index-constraint_002c-matching"></a>
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<p>This is called a <em>matching constraint</em> and what it really means is
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that the assembler has only a single operand that fills two roles
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considered separate in the RTL insn. For example, an add insn has two
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input operands and one output operand in the RTL, but on most CISC
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machines an add instruction really has only two operands, one of them an
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input-output operand:
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</p>
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<div class="smallexample">
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<pre class="smallexample">addl #35,r12
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</pre></div>
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<p>Matching constraints are used in these circumstances.
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More precisely, the two operands that match must include one input-only
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operand and one output-only operand. Moreover, the digit must be a
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smaller number than the number of the operand that uses it in the
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constraint.
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</p>
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<p>For operands to match in a particular case usually means that they
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are identical-looking RTL expressions. But in a few special cases
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specific kinds of dissimilarity are allowed. For example, <code>*x</code>
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as an input operand will match <code>*x++</code> as an output operand.
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For proper results in such cases, the output template should always
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use the output-operand’s number when printing the operand.
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</p>
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<a name="index-load-address-instruction"></a>
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<a name="index-push-address-instruction"></a>
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<a name="index-address-constraints"></a>
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<a name="index-p-in-constraint"></a>
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</dd>
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<dt>‘<samp>p</samp>’</dt>
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<dd><p>An operand that is a valid memory address is allowed. This is
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for “load address” and “push address” instructions.
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</p>
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<a name="index-address_005foperand-1"></a>
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<p>‘<samp>p</samp>’ in the constraint must be accompanied by <code>address_operand</code>
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as the predicate in the <code>match_operand</code>. This predicate interprets
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the mode specified in the <code>match_operand</code> as the mode of the memory
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reference for which the address would be valid.
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</p>
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<a name="index-other-register-constraints"></a>
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<a name="index-extensible-constraints"></a>
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</dd>
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<dt><var>other-letters</var></dt>
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<dd><p>Other letters can be defined in machine-dependent fashion to stand for
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particular classes of registers or other arbitrary operand types.
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‘<samp>d</samp>’, ‘<samp>a</samp>’ and ‘<samp>f</samp>’ are defined on the 68000/68020 to stand
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for data, address and floating point registers.
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</p></dd>
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</dl>
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<p>In order to have valid assembler code, each operand must satisfy
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its constraint. But a failure to do so does not prevent the pattern
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from applying to an insn. Instead, it directs the compiler to modify
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the code so that the constraint will be satisfied. Usually this is
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done by copying an operand into a register.
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</p>
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<p>Contrast, therefore, the two instruction patterns that follow:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn ""
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[(set (match_operand:SI 0 "general_operand" "=r")
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(plus:SI (match_dup 0)
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(match_operand:SI 1 "general_operand" "r")))]
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""
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"…")
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</pre></div>
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<p>which has two operands, one of which must appear in two places, and
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</p>
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<div class="smallexample">
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<pre class="smallexample">(define_insn ""
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[(set (match_operand:SI 0 "general_operand" "=r")
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(plus:SI (match_operand:SI 1 "general_operand" "0")
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(match_operand:SI 2 "general_operand" "r")))]
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""
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"…")
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</pre></div>
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<p>which has three operands, two of which are required by a constraint to be
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identical. If we are considering an insn of the form
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</p>
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<div class="smallexample">
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<pre class="smallexample">(insn <var>n</var> <var>prev</var> <var>next</var>
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(set (reg:SI 3)
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(plus:SI (reg:SI 6) (reg:SI 109)))
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…)
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</pre></div>
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<p>the first pattern would not apply at all, because this insn does not
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contain two identical subexpressions in the right place. The pattern would
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say, “That does not look like an add instruction; try other patterns”.
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The second pattern would say, “Yes, that’s an add instruction, but there
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is something wrong with it”. It would direct the reload pass of the
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compiler to generate additional insns to make the constraint true. The
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results might look like this:
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</p>
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<div class="smallexample">
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<pre class="smallexample">(insn <var>n2</var> <var>prev</var> <var>n</var>
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(set (reg:SI 3) (reg:SI 6))
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…)
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(insn <var>n</var> <var>n2</var> <var>next</var>
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(set (reg:SI 3)
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(plus:SI (reg:SI 3) (reg:SI 109)))
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…)
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</pre></div>
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<p>It is up to you to make sure that each operand, in each pattern, has
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constraints that can handle any RTL expression that could be present for
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that operand. (When multiple alternatives are in use, each pattern must,
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for each possible combination of operand expressions, have at least one
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alternative which can handle that combination of operands.) The
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constraints don’t need to <em>allow</em> any possible operand—when this is
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the case, they do not constrain—but they must at least point the way to
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reloading any possible operand so that it will fit.
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</p>
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<ul>
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<li> If the constraint accepts whatever operands the predicate permits,
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there is no problem: reloading is never necessary for this operand.
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<p>For example, an operand whose constraints permit everything except
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registers is safe provided its predicate rejects registers.
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</p>
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<p>An operand whose predicate accepts only constant values is safe
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provided its constraints include the letter ‘<samp>i</samp>’. If any possible
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constant value is accepted, then nothing less than ‘<samp>i</samp>’ will do;
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if the predicate is more selective, then the constraints may also be
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more selective.
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</p>
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</li><li> Any operand expression can be reloaded by copying it into a register.
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So if an operand’s constraints allow some kind of register, it is
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certain to be safe. It need not permit all classes of registers; the
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compiler knows how to copy a register into another register of the
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proper class in order to make an instruction valid.
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</li><li> <a name="index-nonoffsettable-memory-reference"></a>
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<a name="index-memory-reference_002c-nonoffsettable"></a>
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A nonoffsettable memory reference can be reloaded by copying the
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address into a register. So if the constraint uses the letter
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‘<samp>o</samp>’, all memory references are taken care of.
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</li><li> A constant operand can be reloaded by allocating space in memory to
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hold it as preinitialized data. Then the memory reference can be used
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in place of the constant. So if the constraint uses the letters
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‘<samp>o</samp>’ or ‘<samp>m</samp>’, constant operands are not a problem.
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</li><li> If the constraint permits a constant and a pseudo register used in an insn
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was not allocated to a hard register and is equivalent to a constant,
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the register will be replaced with the constant. If the predicate does
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not permit a constant and the insn is re-recognized for some reason, the
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compiler will crash. Thus the predicate must always recognize any
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objects allowed by the constraint.
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</li></ul>
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<p>If the operand’s predicate can recognize registers, but the constraint does
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not permit them, it can make the compiler crash. When this operand happens
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to be a register, the reload pass will be stymied, because it does not know
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how to copy a register temporarily into memory.
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</p>
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<p>If the predicate accepts a unary operator, the constraint applies to the
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operand. For example, the MIPS processor at ISA level 3 supports an
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instruction which adds two registers in <code>SImode</code> to produce a
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<code>DImode</code> result, but only if the registers are correctly sign
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extended. This predicate for the input operands accepts a
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<code>sign_extend</code> of an <code>SImode</code> register. Write the constraint
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|
to indicate the type of register that is required for the operand of the
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<code>sign_extend</code>.
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</p>
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<hr>
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<p>
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Next: <a href="Multi_002dAlternative.html#Multi_002dAlternative" accesskey="n" rel="next">Multi-Alternative</a>, Up: <a href="Constraints.html#Constraints" accesskey="u" rel="up">Constraints</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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