110 lines
4.7 KiB
HTML
110 lines
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HTML
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<title>GNU Compiler Collection (GCC) Internals: MIPS Coprocessors</title>
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<a name="MIPS-Coprocessors"></a>
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<p>
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Next: <a href="PCH-Target.html#PCH-Target" accesskey="n" rel="next">PCH Target</a>, Previous: <a href="Emulated-TLS.html#Emulated-TLS" accesskey="p" rel="prev">Emulated TLS</a>, Up: <a href="Target-Macros.html#Target-Macros" accesskey="u" rel="up">Target Macros</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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<hr>
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<a name="Defining-coprocessor-specifics-for-MIPS-targets_002e"></a>
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<h3 class="section">17.26 Defining coprocessor specifics for MIPS targets.</h3>
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<a name="index-MIPS-coprocessor_002ddefinition-macros"></a>
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<p>The MIPS specification allows MIPS implementations to have as many as 4
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coprocessors, each with as many as 32 private registers. GCC supports
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accessing these registers and transferring values between the registers
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and memory using asm-ized variables. For example:
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</p>
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<div class="smallexample">
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<pre class="smallexample"> register unsigned int cp0count asm ("c0r1");
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unsigned int d;
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d = cp0count + 3;
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</pre></div>
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<p>(“c0r1” is the default name of register 1 in coprocessor 0; alternate
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names may be added as described below, or the default names may be
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overridden entirely in <code>SUBTARGET_CONDITIONAL_REGISTER_USAGE</code>.)
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</p>
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<p>Coprocessor registers are assumed to be epilogue-used; sets to them will
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be preserved even if it does not appear that the register is used again
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later in the function.
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</p>
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<p>Another note: according to the MIPS spec, coprocessor 1 (if present) is
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the FPU. One accesses COP1 registers through standard mips
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floating-point support; they are not included in this mechanism.
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</p>
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