356 lines
18 KiB
HTML
356 lines
18 KiB
HTML
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- This file documents the GNU linker LD
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(Linaro_Binutils-2017.02)
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version 2.27.0.
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Copyright (C) 1991-2016 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled "GNU Free Documentation License". -->
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<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>LD: ARM</title>
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<meta name="description" content="LD: ARM">
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<meta name="keywords" content="LD: ARM">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="LD-Index.html#LD-Index" rel="index" title="LD Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Machine-Dependent.html#Machine-Dependent" rel="up" title="Machine Dependent">
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<link href="HPPA-ELF32.html#HPPA-ELF32" rel="next" title="HPPA ELF32">
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<link href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" rel="prev" title="M68HC11/68HC12">
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<style type="text/css">
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kbd {font-style:oblique}
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pre.display {font-family: inherit}
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pre.format {font-family: inherit}
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pre.smalldisplay {font-family: inherit; font-size: smaller}
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pre.smalllisp {font-size: smaller}
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span.roman {font-family:serif; font-weight:normal}
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span.sansserif {font-family:sans-serif; font-weight:normal}
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ul.no-bullet {list-style: none}
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-->
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</style>
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</head>
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="ARM"></a>
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<div class="header">
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<p>
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Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="prev">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="ld-and-the-ARM-family"></a>
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<h3 class="section">4.4 <code>ld</code> and the ARM family</h3>
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<a name="index-ARM-interworking-support"></a>
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<a name="index-_002d_002dsupport_002dold_002dcode"></a>
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<p>For the ARM, <code>ld</code> will generate code stubs to allow functions calls
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between ARM and Thumb code. These stubs only work with code that has
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been compiled and assembled with the ‘<samp>-mthumb-interwork</samp>’ command
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line option. If it is necessary to link with old ARM object files or
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libraries, which have not been compiled with the -mthumb-interwork
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option then the ‘<samp>--support-old-code</samp>’ command line switch should be
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given to the linker. This will make it generate larger stub functions
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which will work with non-interworking aware ARM code. Note, however,
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the linker does not support generating stubs for function calls to
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non-interworking aware Thumb code.
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</p>
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<a name="index-thumb-entry-point"></a>
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<a name="index-entry-point_002c-thumb"></a>
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<a name="index-_002d_002dthumb_002dentry_003dentry"></a>
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<p>The ‘<samp>--thumb-entry</samp>’ switch is a duplicate of the generic
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‘<samp>--entry</samp>’ switch, in that it sets the program’s starting address.
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But it also sets the bottom bit of the address, so that it can be
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branched to using a BX instruction, and the program will start
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executing in Thumb mode straight away.
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</p>
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<a name="index-PE-import-table-prefixing"></a>
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<a name="index-_002d_002duse_002dnul_002dprefixed_002dimport_002dtables"></a>
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<p>The ‘<samp>--use-nul-prefixed-import-tables</samp>’ switch is specifying, that
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the import tables idata4 and idata5 have to be generated with a zero
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element prefix for import libraries. This is the old style to generate
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import tables. By default this option is turned off.
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</p>
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<a name="index-BE8"></a>
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<a name="index-_002d_002dbe8"></a>
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<p>The ‘<samp>--be8</samp>’ switch instructs <code>ld</code> to generate BE8 format
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executables. This option is only valid when linking big-endian
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objects - ie ones which have been assembled with the <samp>-EB</samp>
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option. The resulting image will contain big-endian data and
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little-endian code.
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</p>
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<a name="index-TARGET1"></a>
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<a name="index-_002d_002dtarget1_002drel"></a>
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<a name="index-_002d_002dtarget1_002dabs"></a>
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<p>The ‘<samp>R_ARM_TARGET1</samp>’ relocation is typically used for entries in the
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‘<samp>.init_array</samp>’ section. It is interpreted as either ‘<samp>R_ARM_REL32</samp>’
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or ‘<samp>R_ARM_ABS32</samp>’, depending on the target. The ‘<samp>--target1-rel</samp>’
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and ‘<samp>--target1-abs</samp>’ switches override the default.
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</p>
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<a name="index-TARGET2"></a>
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<a name="index-_002d_002dtarget2_003dtype"></a>
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<p>The ‘<samp>--target2=type</samp>’ switch overrides the default definition of the
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‘<samp>R_ARM_TARGET2</samp>’ relocation. Valid values for ‘<samp>type</samp>’, their
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meanings, and target defaults are as follows:
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</p><dl compact="compact">
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<dt>‘<samp>rel</samp>’</dt>
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<dd><p>‘<samp>R_ARM_REL32</samp>’ (arm*-*-elf, arm*-*-eabi)
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</p></dd>
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<dt>‘<samp>abs</samp>’</dt>
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<dd><p>‘<samp>R_ARM_ABS32</samp>’ (arm*-*-symbianelf)
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</p></dd>
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<dt>‘<samp>got-rel</samp>’</dt>
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<dd><p>‘<samp>R_ARM_GOT_PREL</samp>’ (arm*-*-linux, arm*-*-*bsd)
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</p></dd>
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</dl>
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<a name="index-FIX_005fV4BX"></a>
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<a name="index-_002d_002dfix_002dv4bx"></a>
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<p>The ‘<samp>R_ARM_V4BX</samp>’ relocation (defined by the ARM AAELF
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specification) enables objects compiled for the ARMv4 architecture to be
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interworking-safe when linked with other objects compiled for ARMv4t, but
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also allows pure ARMv4 binaries to be built from the same ARMv4 objects.
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</p>
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<p>In the latter case, the switch <samp>--fix-v4bx</samp> must be passed to the
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linker, which causes v4t <code>BX rM</code> instructions to be rewritten as
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<code>MOV PC,rM</code>, since v4 processors do not have a <code>BX</code> instruction.
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</p>
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<p>In the former case, the switch should not be used, and ‘<samp>R_ARM_V4BX</samp>’
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relocations are ignored.
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</p>
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<a name="index-FIX_005fV4BX_005fINTERWORKING"></a>
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<a name="index-_002d_002dfix_002dv4bx_002dinterworking"></a>
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<p>Replace <code>BX rM</code> instructions identified by ‘<samp>R_ARM_V4BX</samp>’
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relocations with a branch to the following veneer:
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</p>
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<div class="smallexample">
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<pre class="smallexample">TST rM, #1
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MOVEQ PC, rM
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BX Rn
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</pre></div>
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<p>This allows generation of libraries/applications that work on ARMv4 cores
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and are still interworking safe. Note that the above veneer clobbers the
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condition flags, so may cause incorrect program behavior in rare cases.
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</p>
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<a name="index-USE_005fBLX"></a>
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<a name="index-_002d_002duse_002dblx"></a>
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<p>The ‘<samp>--use-blx</samp>’ switch enables the linker to use ARM/Thumb
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BLX instructions (available on ARMv5t and above) in various
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situations. Currently it is used to perform calls via the PLT from Thumb
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code using BLX rather than using BX and a mode-switching stub before
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each PLT entry. This should lead to such calls executing slightly faster.
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</p>
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<p>This option is enabled implicitly for SymbianOS, so there is no need to
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specify it if you are using that target.
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</p>
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<a name="index-VFP11_005fDENORM_005fFIX"></a>
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<a name="index-_002d_002dvfp11_002ddenorm_002dfix"></a>
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<p>The ‘<samp>--vfp11-denorm-fix</samp>’ switch enables a link-time workaround for a
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bug in certain VFP11 coprocessor hardware, which sometimes allows
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instructions with denorm operands (which must be handled by support code)
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to have those operands overwritten by subsequent instructions before
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the support code can read the intended values.
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</p>
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<p>The bug may be avoided in scalar mode if you allow at least one
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intervening instruction between a VFP11 instruction which uses a register
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and another instruction which writes to the same register, or at least two
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intervening instructions if vector mode is in use. The bug only affects
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full-compliance floating-point mode: you do not need this workaround if
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you are using "runfast" mode. Please contact ARM for further details.
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</p>
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<p>If you know you are using buggy VFP11 hardware, you can
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enable this workaround by specifying the linker option
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‘<samp>--vfp-denorm-fix=scalar</samp>’ if you are using the VFP11 scalar
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mode only, or ‘<samp>--vfp-denorm-fix=vector</samp>’ if you are using
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vector mode (the latter also works for scalar code). The default is
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‘<samp>--vfp-denorm-fix=none</samp>’.
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</p>
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<p>If the workaround is enabled, instructions are scanned for
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potentially-troublesome sequences, and a veneer is created for each
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such sequence which may trigger the erratum. The veneer consists of the
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first instruction of the sequence and a branch back to the subsequent
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instruction. The original instruction is then replaced with a branch to
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the veneer. The extra cycles required to call and return from the veneer
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are sufficient to avoid the erratum in both the scalar and vector cases.
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</p>
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<a name="index-ARM1176-erratum-workaround"></a>
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<a name="index-_002d_002dfix_002darm1176"></a>
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<a name="index-_002d_002dno_002dfix_002darm1176"></a>
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<p>The ‘<samp>--fix-arm1176</samp>’ switch enables a link-time workaround for an erratum
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in certain ARM1176 processors. The workaround is enabled by default if you
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are targeting ARM v6 (excluding ARM v6T2) or earlier. It can be disabled
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unconditionally by specifying ‘<samp>--no-fix-arm1176</samp>’.
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</p>
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<p>Further information is available in the “ARM1176JZ-S and ARM1176JZF-S
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Programmer Advice Notice” available on the ARM documentation website at:
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http://infocenter.arm.com/.
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</p>
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<a name="index-STM32L4xx-erratum-workaround"></a>
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<a name="index-_002d_002dfix_002dstm32l4xx_002d629360"></a>
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<p>The ‘<samp>--fix-stm32l4xx-629360</samp>’ switch enables a link-time
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workaround for a bug in the bus matrix / memory controller for some of
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the STM32 Cortex-M4 based products (STM32L4xx). When accessing
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off-chip memory via the affected bus for bus reads of 9 words or more,
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the bus can generate corrupt data and/or abort. These are only
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core-initiated accesses (not DMA), and might affect any access:
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integer loads such as LDM, POP and floating-point loads such as VLDM,
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VPOP. Stores are not affected.
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</p>
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<p>The bug can be avoided by splitting memory accesses into the
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necessary chunks to keep bus reads below 8 words.
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</p>
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<p>The workaround is not enabled by default, this is equivalent to use
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‘<samp>--fix-stm32l4xx-629360=none</samp>’. If you know you are using buggy
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STM32L4xx hardware, you can enable the workaround by specifying the
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linker option ‘<samp>--fix-stm32l4xx-629360</samp>’, or the equivalent
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‘<samp>--fix-stm32l4xx-629360=default</samp>’.
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</p>
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<p>If the workaround is enabled, instructions are scanned for
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potentially-troublesome sequences, and a veneer is created for each
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such sequence which may trigger the erratum. The veneer consists in a
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replacement sequence emulating the behaviour of the original one and a
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branch back to the subsequent instruction. The original instruction is
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then replaced with a branch to the veneer.
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</p>
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<p>The workaround does not always preserve the memory access order for
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the LDMDB instruction, when the instruction loads the PC.
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</p>
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<p>The workaround is not able to handle problematic instructions when
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they are in the middle of an IT block, since a branch is not allowed
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there. In that case, the linker reports a warning and no replacement
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occurs.
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</p>
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<p>The workaround is not able to replace problematic instructions with a
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PC-relative branch instruction if the ‘<samp>.text</samp>’ section is too
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large. In that case, when the branch that replaces the original code
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cannot be encoded, the linker reports a warning and no replacement
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occurs.
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</p>
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<a name="index-NO_005fENUM_005fSIZE_005fWARNING"></a>
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<a name="index-_002d_002dno_002denum_002dsize_002dwarning"></a>
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<p>The <samp>--no-enum-size-warning</samp> switch prevents the linker from
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warning when linking object files that specify incompatible EABI
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enumeration size attributes. For example, with this switch enabled,
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linking of an object file using 32-bit enumeration values with another
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using enumeration values fitted into the smallest possible space will
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not be diagnosed.
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</p>
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<a name="index-NO_005fWCHAR_005fSIZE_005fWARNING"></a>
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<a name="index-_002d_002dno_002dwchar_002dsize_002dwarning"></a>
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<p>The <samp>--no-wchar-size-warning</samp> switch prevents the linker from
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warning when linking object files that specify incompatible EABI
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<code>wchar_t</code> size attributes. For example, with this switch enabled,
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linking of an object file using 32-bit <code>wchar_t</code> values with another
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using 16-bit <code>wchar_t</code> values will not be diagnosed.
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</p>
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<a name="index-PIC_005fVENEER"></a>
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<a name="index-_002d_002dpic_002dveneer"></a>
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|
|
<p>The ‘<samp>--pic-veneer</samp>’ switch makes the linker use PIC sequences for
|
||
|
|
ARM/Thumb interworking veneers, even if the rest of the binary
|
||
|
|
is not PIC. This avoids problems on uClinux targets where
|
||
|
|
‘<samp>--emit-relocs</samp>’ is used to generate relocatable binaries.
|
||
|
|
</p>
|
||
|
|
<a name="index-STUB_005fGROUP_005fSIZE"></a>
|
||
|
|
<a name="index-_002d_002dstub_002dgroup_002dsize_003dN"></a>
|
||
|
|
<p>The linker will automatically generate and insert small sequences of
|
||
|
|
code into a linked ARM ELF executable whenever an attempt is made to
|
||
|
|
perform a function call to a symbol that is too far away. The
|
||
|
|
placement of these sequences of instructions - called stubs - is
|
||
|
|
controlled by the command line option <samp>--stub-group-size=N</samp>.
|
||
|
|
The placement is important because a poor choice can create a need for
|
||
|
|
duplicate stubs, increasing the code size. The linker will try to
|
||
|
|
group stubs together in order to reduce interruptions to the flow of
|
||
|
|
code, but it needs guidance as to how big these groups should be and
|
||
|
|
where they should be placed.
|
||
|
|
</p>
|
||
|
|
<p>The value of ‘<samp>N</samp>’, the parameter to the
|
||
|
|
<samp>--stub-group-size=</samp> option controls where the stub groups are
|
||
|
|
placed. If it is negative then all stubs are placed after the first
|
||
|
|
branch that needs them. If it is positive then the stubs can be
|
||
|
|
placed either before or after the branches that need them. If the
|
||
|
|
value of ‘<samp>N</samp>’ is 1 (either +1 or -1) then the linker will choose
|
||
|
|
exactly where to place groups of stubs, using its built in heuristics.
|
||
|
|
A value of ‘<samp>N</samp>’ greater than 1 (or smaller than -1) tells the
|
||
|
|
linker that a single group of stubs can service at most ‘<samp>N</samp>’ bytes
|
||
|
|
from the input sections.
|
||
|
|
</p>
|
||
|
|
<p>The default, if <samp>--stub-group-size=</samp> is not specified, is
|
||
|
|
‘<samp>N = +1</samp>’.
|
||
|
|
</p>
|
||
|
|
<p>Farcalls stubs insertion is fully supported for the ARM-EABI target
|
||
|
|
only, because it relies on object files properties not present
|
||
|
|
otherwise.
|
||
|
|
</p>
|
||
|
|
<a name="index-Cortex_002dA8-erratum-workaround"></a>
|
||
|
|
<a name="index-_002d_002dfix_002dcortex_002da8"></a>
|
||
|
|
<a name="index-_002d_002dno_002dfix_002dcortex_002da8"></a>
|
||
|
|
<p>The ‘<samp>--fix-cortex-a8</samp>’ switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying ‘<samp>--fix-cortex-a8</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a8</samp>’.
|
||
|
|
</p>
|
||
|
|
<p>The erratum only affects Thumb-2 code. Please contact ARM for further details.
|
||
|
|
</p>
|
||
|
|
<a name="index-Cortex_002dA53-erratum-835769-workaround"></a>
|
||
|
|
<a name="index-_002d_002dfix_002dcortex_002da53_002d835769"></a>
|
||
|
|
<a name="index-_002d_002dno_002dfix_002dcortex_002da53_002d835769"></a>
|
||
|
|
<p>The ‘<samp>--fix-cortex-a53-835769</samp>’ switch enables a link-time workaround for erratum 835769 present on certain early revisions of Cortex-A53 processors. The workaround is disabled by default. It can be enabled by specifying ‘<samp>--fix-cortex-a53-835769</samp>’, or disabled unconditionally by specifying ‘<samp>--no-fix-cortex-a53-835769</samp>’.
|
||
|
|
</p>
|
||
|
|
<p>Please contact ARM for further details.
|
||
|
|
</p>
|
||
|
|
<a name="index-_002d_002dmerge_002dexidx_002dentries"></a>
|
||
|
|
<a name="index-_002d_002dno_002dmerge_002dexidx_002dentries-1"></a>
|
||
|
|
<a name="index-Merging-exidx-entries"></a>
|
||
|
|
<p>The ‘<samp>--no-merge-exidx-entries</samp>’ switch disables the merging of adjacent exidx entries in debuginfo.
|
||
|
|
</p>
|
||
|
|
<a name="index-_002d_002dlong_002dplt"></a>
|
||
|
|
<a name="index-32_002dbit-PLT-entries"></a>
|
||
|
|
<p>The ‘<samp>--long-plt</samp>’ option enables the use of 16 byte PLT entries
|
||
|
|
which support up to 4Gb of code. The default is to use 12 byte PLT
|
||
|
|
entries which only support 512Mb of code.
|
||
|
|
</p>
|
||
|
|
<a name="index-_002d_002dno_002dapply_002ddynamic_002drelocs"></a>
|
||
|
|
<a name="index-AArch64-rela-addend"></a>
|
||
|
|
<p>The ‘<samp>--no-apply-dynamic-relocs</samp>’ option makes AArch64 linker do not apply
|
||
|
|
link-time values for dynamic relocations.
|
||
|
|
</p>
|
||
|
|
|
||
|
|
|
||
|
|
<hr>
|
||
|
|
<div class="header">
|
||
|
|
<p>
|
||
|
|
Next: <a href="HPPA-ELF32.html#HPPA-ELF32" accesskey="n" rel="next">HPPA ELF32</a>, Previous: <a href="M68HC11_002f68HC12.html#M68HC11_002f68HC12" accesskey="p" rel="prev">M68HC11/68HC12</a>, Up: <a href="Machine-Dependent.html#Machine-Dependent" accesskey="u" rel="up">Machine Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="LD-Index.html#LD-Index" title="Index" rel="index">Index</a>]</p>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
</body>
|
||
|
|
</html>
|