408 lines
17 KiB
HTML
408 lines
17 KiB
HTML
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- Copyright (C) 1988-2016 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3 or
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any later version published by the Free Software Foundation; with the
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Invariant Sections being "Funding Free Software", the Front-Cover
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Texts being (a) (see below), and with the Back-Cover Texts being (b)
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(see below). A copy of the license is included in the section entitled
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"GNU Free Documentation License".
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(a) The FSF's Front-Cover Text is:
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A GNU Manual
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(b) The FSF's Back-Cover Text is:
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You have freedom to copy and modify this GNU Manual, like GNU
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software. Copies published by the Free Software Foundation raise
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funds for GNU development. -->
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<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Using the GNU Compiler Collection (GCC): IA-64 Options</title>
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<meta name="description" content="Using the GNU Compiler Collection (GCC): IA-64 Options">
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<meta name="keywords" content="Using the GNU Compiler Collection (GCC): IA-64 Options">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="Option-Index.html#Option-Index" rel="index" title="Option Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Submodel-Options.html#Submodel-Options" rel="up" title="Submodel Options">
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<link href="LM32-Options.html#LM32-Options" rel="next" title="LM32 Options">
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<link href="HPPA-Options.html#HPPA-Options" rel="prev" title="HPPA Options">
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<style type="text/css">
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</style>
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</head>
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="IA_002d64-Options"></a>
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<div class="header">
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<p>
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Next: <a href="LM32-Options.html#LM32-Options" accesskey="n" rel="next">LM32 Options</a>, Previous: <a href="HPPA-Options.html#HPPA-Options" accesskey="p" rel="prev">HPPA Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="IA_002d64-Options-1"></a>
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<h4 class="subsection">3.18.18 IA-64 Options</h4>
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<a name="index-IA_002d64-Options"></a>
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<p>These are the ‘<samp>-m</samp>’ options defined for the Intel IA-64 architecture.
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</p>
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<dl compact="compact">
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<dt><code>-mbig-endian</code></dt>
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<dd><a name="index-mbig_002dendian-4"></a>
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<p>Generate code for a big-endian target. This is the default for HP-UX.
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</p>
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</dd>
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<dt><code>-mlittle-endian</code></dt>
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<dd><a name="index-mlittle_002dendian-4"></a>
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<p>Generate code for a little-endian target. This is the default for AIX5
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and GNU/Linux.
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</p>
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</dd>
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<dt><code>-mgnu-as</code></dt>
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<dt><code>-mno-gnu-as</code></dt>
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<dd><a name="index-mgnu_002das"></a>
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<a name="index-mno_002dgnu_002das"></a>
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<p>Generate (or don’t) code for the GNU assembler. This is the default.
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</p>
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</dd>
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<dt><code>-mgnu-ld</code></dt>
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<dt><code>-mno-gnu-ld</code></dt>
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<dd><a name="index-mgnu_002dld-1"></a>
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<a name="index-mno_002dgnu_002dld"></a>
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<p>Generate (or don’t) code for the GNU linker. This is the default.
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</p>
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</dd>
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<dt><code>-mno-pic</code></dt>
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<dd><a name="index-mno_002dpic"></a>
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<p>Generate code that does not use a global pointer register. The result
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is not position independent code, and violates the IA-64 ABI.
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</p>
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</dd>
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<dt><code>-mvolatile-asm-stop</code></dt>
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<dt><code>-mno-volatile-asm-stop</code></dt>
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<dd><a name="index-mvolatile_002dasm_002dstop"></a>
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<a name="index-mno_002dvolatile_002dasm_002dstop"></a>
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<p>Generate (or don’t) a stop bit immediately before and after volatile asm
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statements.
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</p>
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</dd>
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<dt><code>-mregister-names</code></dt>
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<dt><code>-mno-register-names</code></dt>
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<dd><a name="index-mregister_002dnames"></a>
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<a name="index-mno_002dregister_002dnames"></a>
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<p>Generate (or don’t) ‘<samp>in</samp>’, ‘<samp>loc</samp>’, and ‘<samp>out</samp>’ register names for
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the stacked registers. This may make assembler output more readable.
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</p>
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</dd>
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<dt><code>-mno-sdata</code></dt>
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<dt><code>-msdata</code></dt>
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<dd><a name="index-mno_002dsdata-1"></a>
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<a name="index-msdata"></a>
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<p>Disable (or enable) optimizations that use the small data section. This may
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be useful for working around optimizer bugs.
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</p>
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</dd>
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<dt><code>-mconstant-gp</code></dt>
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<dd><a name="index-mconstant_002dgp"></a>
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<p>Generate code that uses a single constant global pointer value. This is
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useful when compiling kernel code.
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</p>
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</dd>
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<dt><code>-mauto-pic</code></dt>
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<dd><a name="index-mauto_002dpic"></a>
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<p>Generate code that is self-relocatable. This implies <samp>-mconstant-gp</samp>.
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This is useful when compiling firmware code.
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</p>
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</dd>
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<dt><code>-minline-float-divide-min-latency</code></dt>
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<dd><a name="index-minline_002dfloat_002ddivide_002dmin_002dlatency"></a>
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<p>Generate code for inline divides of floating-point values
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using the minimum latency algorithm.
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</p>
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</dd>
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<dt><code>-minline-float-divide-max-throughput</code></dt>
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<dd><a name="index-minline_002dfloat_002ddivide_002dmax_002dthroughput"></a>
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<p>Generate code for inline divides of floating-point values
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using the maximum throughput algorithm.
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</p>
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</dd>
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<dt><code>-mno-inline-float-divide</code></dt>
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<dd><a name="index-mno_002dinline_002dfloat_002ddivide"></a>
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<p>Do not generate inline code for divides of floating-point values.
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</p>
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</dd>
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<dt><code>-minline-int-divide-min-latency</code></dt>
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<dd><a name="index-minline_002dint_002ddivide_002dmin_002dlatency"></a>
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<p>Generate code for inline divides of integer values
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using the minimum latency algorithm.
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</p>
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</dd>
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<dt><code>-minline-int-divide-max-throughput</code></dt>
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<dd><a name="index-minline_002dint_002ddivide_002dmax_002dthroughput"></a>
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<p>Generate code for inline divides of integer values
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using the maximum throughput algorithm.
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</p>
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</dd>
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<dt><code>-mno-inline-int-divide</code></dt>
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<dd><a name="index-mno_002dinline_002dint_002ddivide"></a>
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<p>Do not generate inline code for divides of integer values.
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</p>
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</dd>
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<dt><code>-minline-sqrt-min-latency</code></dt>
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<dd><a name="index-minline_002dsqrt_002dmin_002dlatency"></a>
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<p>Generate code for inline square roots
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using the minimum latency algorithm.
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</p>
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</dd>
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<dt><code>-minline-sqrt-max-throughput</code></dt>
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<dd><a name="index-minline_002dsqrt_002dmax_002dthroughput"></a>
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<p>Generate code for inline square roots
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using the maximum throughput algorithm.
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</p>
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</dd>
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<dt><code>-mno-inline-sqrt</code></dt>
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<dd><a name="index-mno_002dinline_002dsqrt"></a>
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<p>Do not generate inline code for <code>sqrt</code>.
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</p>
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</dd>
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<dt><code>-mfused-madd</code></dt>
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<dt><code>-mno-fused-madd</code></dt>
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<dd><a name="index-mfused_002dmadd"></a>
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<a name="index-mno_002dfused_002dmadd"></a>
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<p>Do (don’t) generate code that uses the fused multiply/add or multiply/subtract
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instructions. The default is to use these instructions.
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</p>
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</dd>
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<dt><code>-mno-dwarf2-asm</code></dt>
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<dt><code>-mdwarf2-asm</code></dt>
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<dd><a name="index-mno_002ddwarf2_002dasm"></a>
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<a name="index-mdwarf2_002dasm"></a>
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<p>Don’t (or do) generate assembler code for the DWARF line number debugging
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info. This may be useful when not using the GNU assembler.
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</p>
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</dd>
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<dt><code>-mearly-stop-bits</code></dt>
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<dt><code>-mno-early-stop-bits</code></dt>
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<dd><a name="index-mearly_002dstop_002dbits"></a>
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<a name="index-mno_002dearly_002dstop_002dbits"></a>
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<p>Allow stop bits to be placed earlier than immediately preceding the
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instruction that triggered the stop bit. This can improve instruction
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scheduling, but does not always do so.
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</p>
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</dd>
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<dt><code>-mfixed-range=<var>register-range</var></code></dt>
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<dd><a name="index-mfixed_002drange-1"></a>
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<p>Generate code treating the given register range as fixed registers.
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A fixed register is one that the register allocator cannot use. This is
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useful when compiling kernel code. A register range is specified as
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two registers separated by a dash. Multiple register ranges can be
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specified separated by a comma.
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</p>
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</dd>
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<dt><code>-mtls-size=<var>tls-size</var></code></dt>
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<dd><a name="index-mtls_002dsize-1"></a>
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<p>Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
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64.
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</p>
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</dd>
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<dt><code>-mtune=<var>cpu-type</var></code></dt>
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<dd><a name="index-mtune-6"></a>
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<p>Tune the instruction scheduling for a particular CPU, Valid values are
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‘<samp>itanium</samp>’, ‘<samp>itanium1</samp>’, ‘<samp>merced</samp>’, ‘<samp>itanium2</samp>’,
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and ‘<samp>mckinley</samp>’.
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</p>
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</dd>
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<dt><code>-milp32</code></dt>
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<dt><code>-mlp64</code></dt>
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<dd><a name="index-milp32"></a>
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<a name="index-mlp64"></a>
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<p>Generate code for a 32-bit or 64-bit environment.
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The 32-bit environment sets int, long and pointer to 32 bits.
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The 64-bit environment sets int to 32 bits and long and pointer
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to 64 bits. These are HP-UX specific flags.
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</p>
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</dd>
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<dt><code>-mno-sched-br-data-spec</code></dt>
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<dt><code>-msched-br-data-spec</code></dt>
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<dd><a name="index-mno_002dsched_002dbr_002ddata_002dspec"></a>
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<a name="index-msched_002dbr_002ddata_002dspec"></a>
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<p>(Dis/En)able data speculative scheduling before reload.
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This results in generation of <code>ld.a</code> instructions and
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the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
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The default setting is disabled.
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</p>
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</dd>
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<dt><code>-msched-ar-data-spec</code></dt>
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<dt><code>-mno-sched-ar-data-spec</code></dt>
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<dd><a name="index-msched_002dar_002ddata_002dspec"></a>
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<a name="index-mno_002dsched_002dar_002ddata_002dspec"></a>
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<p>(En/Dis)able data speculative scheduling after reload.
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This results in generation of <code>ld.a</code> instructions and
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the corresponding check instructions (<code>ld.c</code> / <code>chk.a</code>).
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The default setting is enabled.
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</p>
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</dd>
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<dt><code>-mno-sched-control-spec</code></dt>
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<dt><code>-msched-control-spec</code></dt>
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<dd><a name="index-mno_002dsched_002dcontrol_002dspec"></a>
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<a name="index-msched_002dcontrol_002dspec"></a>
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<p>(Dis/En)able control speculative scheduling. This feature is
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available only during region scheduling (i.e. before reload).
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This results in generation of the <code>ld.s</code> instructions and
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the corresponding check instructions <code>chk.s</code>.
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The default setting is disabled.
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</p>
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</dd>
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<dt><code>-msched-br-in-data-spec</code></dt>
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<dt><code>-mno-sched-br-in-data-spec</code></dt>
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<dd><a name="index-msched_002dbr_002din_002ddata_002dspec"></a>
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<a name="index-mno_002dsched_002dbr_002din_002ddata_002dspec"></a>
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<p>(En/Dis)able speculative scheduling of the instructions that
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are dependent on the data speculative loads before reload.
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This is effective only with <samp>-msched-br-data-spec</samp> enabled.
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The default setting is enabled.
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</p>
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</dd>
|
||
|
|
<dt><code>-msched-ar-in-data-spec</code></dt>
|
||
|
|
<dt><code>-mno-sched-ar-in-data-spec</code></dt>
|
||
|
|
<dd><a name="index-msched_002dar_002din_002ddata_002dspec"></a>
|
||
|
|
<a name="index-mno_002dsched_002dar_002din_002ddata_002dspec"></a>
|
||
|
|
<p>(En/Dis)able speculative scheduling of the instructions that
|
||
|
|
are dependent on the data speculative loads after reload.
|
||
|
|
This is effective only with <samp>-msched-ar-data-spec</samp> enabled.
|
||
|
|
The default setting is enabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-in-control-spec</code></dt>
|
||
|
|
<dt><code>-mno-sched-in-control-spec</code></dt>
|
||
|
|
<dd><a name="index-msched_002din_002dcontrol_002dspec"></a>
|
||
|
|
<a name="index-mno_002dsched_002din_002dcontrol_002dspec"></a>
|
||
|
|
<p>(En/Dis)able speculative scheduling of the instructions that
|
||
|
|
are dependent on the control speculative loads.
|
||
|
|
This is effective only with <samp>-msched-control-spec</samp> enabled.
|
||
|
|
The default setting is enabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-sched-prefer-non-data-spec-insns</code></dt>
|
||
|
|
<dt><code>-msched-prefer-non-data-spec-insns</code></dt>
|
||
|
|
<dd><a name="index-mno_002dsched_002dprefer_002dnon_002ddata_002dspec_002dinsns"></a>
|
||
|
|
<a name="index-msched_002dprefer_002dnon_002ddata_002dspec_002dinsns"></a>
|
||
|
|
<p>If enabled, data-speculative instructions are chosen for schedule
|
||
|
|
only if there are no other choices at the moment. This makes
|
||
|
|
the use of the data speculation much more conservative.
|
||
|
|
The default setting is disabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-sched-prefer-non-control-spec-insns</code></dt>
|
||
|
|
<dt><code>-msched-prefer-non-control-spec-insns</code></dt>
|
||
|
|
<dd><a name="index-mno_002dsched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns"></a>
|
||
|
|
<a name="index-msched_002dprefer_002dnon_002dcontrol_002dspec_002dinsns"></a>
|
||
|
|
<p>If enabled, control-speculative instructions are chosen for schedule
|
||
|
|
only if there are no other choices at the moment. This makes
|
||
|
|
the use of the control speculation much more conservative.
|
||
|
|
The default setting is disabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-mno-sched-count-spec-in-critical-path</code></dt>
|
||
|
|
<dt><code>-msched-count-spec-in-critical-path</code></dt>
|
||
|
|
<dd><a name="index-mno_002dsched_002dcount_002dspec_002din_002dcritical_002dpath"></a>
|
||
|
|
<a name="index-msched_002dcount_002dspec_002din_002dcritical_002dpath"></a>
|
||
|
|
<p>If enabled, speculative dependencies are considered during
|
||
|
|
computation of the instructions priorities. This makes the use of the
|
||
|
|
speculation a bit more conservative.
|
||
|
|
The default setting is disabled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-spec-ldc</code></dt>
|
||
|
|
<dd><a name="index-msched_002dspec_002dldc"></a>
|
||
|
|
<p>Use a simple data speculation check. This option is on by default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-control-spec-ldc</code></dt>
|
||
|
|
<dd><a name="index-msched_002dspec_002dldc-1"></a>
|
||
|
|
<p>Use a simple check for control speculation. This option is on by default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-stop-bits-after-every-cycle</code></dt>
|
||
|
|
<dd><a name="index-msched_002dstop_002dbits_002dafter_002devery_002dcycle"></a>
|
||
|
|
<p>Place a stop bit after every cycle when scheduling. This option is on
|
||
|
|
by default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-fp-mem-deps-zero-cost</code></dt>
|
||
|
|
<dd><a name="index-msched_002dfp_002dmem_002ddeps_002dzero_002dcost"></a>
|
||
|
|
<p>Assume that floating-point stores and loads are not likely to cause a conflict
|
||
|
|
when placed into the same instruction group. This option is disabled by
|
||
|
|
default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msel-sched-dont-check-control-spec</code></dt>
|
||
|
|
<dd><a name="index-msel_002dsched_002ddont_002dcheck_002dcontrol_002dspec"></a>
|
||
|
|
<p>Generate checks for control speculation in selective scheduling.
|
||
|
|
This flag is disabled by default.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-max-memory-insns=<var>max-insns</var></code></dt>
|
||
|
|
<dd><a name="index-msched_002dmax_002dmemory_002dinsns"></a>
|
||
|
|
<p>Limit on the number of memory insns per instruction group, giving lower
|
||
|
|
priority to subsequent memory insns attempting to schedule in the same
|
||
|
|
instruction group. Frequently useful to prevent cache bank conflicts.
|
||
|
|
The default value is 1.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
<dt><code>-msched-max-memory-insns-hard-limit</code></dt>
|
||
|
|
<dd><a name="index-msched_002dmax_002dmemory_002dinsns_002dhard_002dlimit"></a>
|
||
|
|
<p>Makes the limit specified by <samp>msched-max-memory-insns</samp> a hard limit,
|
||
|
|
disallowing more than that number in an instruction group.
|
||
|
|
Otherwise, the limit is “soft”, meaning that non-memory operations
|
||
|
|
are preferred when the limit is reached, but memory operations may still
|
||
|
|
be scheduled.
|
||
|
|
</p>
|
||
|
|
</dd>
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<hr>
|
||
|
|
<div class="header">
|
||
|
|
<p>
|
||
|
|
Next: <a href="LM32-Options.html#LM32-Options" accesskey="n" rel="next">LM32 Options</a>, Previous: <a href="HPPA-Options.html#HPPA-Options" accesskey="p" rel="prev">HPPA Options</a>, Up: <a href="Submodel-Options.html#Submodel-Options" accesskey="u" rel="up">Submodel Options</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
</body>
|
||
|
|
</html>
|