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<!-- This file documents the GNU Assembler "as".
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Copyright (C) 1991-2016 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Using as: Sparc-Constants</title>
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<meta name="description" content="Using as: Sparc-Constants">
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<meta name="keywords" content="Using as: Sparc-Constants">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Sparc_002dSyntax.html#Sparc_002dSyntax" rel="up" title="Sparc-Syntax">
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<link href="Sparc_002dRelocs.html#Sparc_002dRelocs" rel="next" title="Sparc-Relocs">
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="Sparc_002dConstants"></a>
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<div class="header">
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<p>
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Next: <a href="Sparc_002dRelocs.html#Sparc_002dRelocs" accesskey="n" rel="next">Sparc-Relocs</a>, Previous: <a href="Sparc_002dRegs.html#Sparc_002dRegs" accesskey="p" rel="prev">Sparc-Regs</a>, Up: <a href="Sparc_002dSyntax.html#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Constants-2"></a>
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<h4 class="subsubsection">9.42.3.3 Constants</h4>
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<a name="index-Sparc-constants"></a>
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<a name="index-constants_002c-Sparc"></a>
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<p>Several Sparc instructions take an immediate operand field for
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which mnemonic names exist. Two such examples are ‘<samp>membar</samp>’
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and ‘<samp>prefetch</samp>’. Another example are the set of V9
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memory access instruction that allow specification of an
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address space identifier.
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</p>
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<p>The ‘<samp>membar</samp>’ instruction specifies a memory barrier that is
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the defined by the operand which is a bitmask. The supported
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mask mnemonics are:
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</p>
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<ul>
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<li> ‘<samp>#Sync</samp>’ requests that all operations (including nonmemory
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reference operations) appearing prior to the <code>membar</code> must have
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been performed and the effects of any exceptions become visible before
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any instructions after the <code>membar</code> may be initiated. This
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corresponds to <code>membar</code> cmask field bit 2.
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</li><li> ‘<samp>#MemIssue</samp>’ requests that all memory reference operations
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appearing prior to the <code>membar</code> must have been performed before
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any memory operation after the <code>membar</code> may be initiated. This
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corresponds to <code>membar</code> cmask field bit 1.
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</li><li> ‘<samp>#Lookaside</samp>’ requests that a store appearing prior to the
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<code>membar</code> must complete before any load following the
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<code>membar</code> referencing the same address can be initiated. This
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corresponds to <code>membar</code> cmask field bit 0.
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</li><li> ‘<samp>#StoreStore</samp>’ defines that the effects of all stores appearing
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prior to the <code>membar</code> instruction must be visible to all
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processors before the effect of any stores following the
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<code>membar</code>. Equivalent to the deprecated <code>stbar</code> instruction.
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This corresponds to <code>membar</code> mmask field bit 3.
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</li><li> ‘<samp>#LoadStore</samp>’ defines all loads appearing prior to the
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<code>membar</code> instruction must have been performed before the effect
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of any stores following the <code>membar</code> is visible to any other
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processor. This corresponds to <code>membar</code> mmask field bit 2.
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</li><li> ‘<samp>#StoreLoad</samp>’ defines that the effects of all stores appearing
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prior to the <code>membar</code> instruction must be visible to all
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processors before loads following the <code>membar</code> may be performed.
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This corresponds to <code>membar</code> mmask field bit 1.
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</li><li> ‘<samp>#LoadLoad</samp>’ defines that all loads appearing prior to the
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<code>membar</code> instruction must have been performed before any loads
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following the <code>membar</code> may be performed. This corresponds to
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<code>membar</code> mmask field bit 0.
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</li></ul>
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<p>These values can be ored together, for example:
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</p>
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<div class="example">
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<pre class="example">membar #Sync
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membar #StoreLoad | #LoadLoad
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membar #StoreLoad | #StoreStore
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</pre></div>
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<p>The <code>prefetch</code> and <code>prefetcha</code> instructions take a prefetch
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function code. The following prefetch function code constant
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mnemonics are available:
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</p>
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<ul>
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<li> ‘<samp>#n_reads</samp>’ requests a prefetch for several reads, and corresponds
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to a prefetch function code of 0.
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<p>‘<samp>#one_read</samp>’ requests a prefetch for one read, and corresponds
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to a prefetch function code of 1.
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</p>
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<p>‘<samp>#n_writes</samp>’ requests a prefetch for several writes (and possibly
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reads), and corresponds to a prefetch function code of 2.
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</p>
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<p>‘<samp>#one_write</samp>’ requests a prefetch for one write, and corresponds
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to a prefetch function code of 3.
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</p>
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<p>‘<samp>#page</samp>’ requests a prefetch page, and corresponds to a prefetch
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function code of 4.
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</p>
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<p>‘<samp>#invalidate</samp>’ requests a prefetch invalidate, and corresponds to
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a prefetch function code of 16.
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</p>
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<p>‘<samp>#unified</samp>’ requests a prefetch to the nearest unified cache, and
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corresponds to a prefetch function code of 17.
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</p>
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<p>‘<samp>#n_reads_strong</samp>’ requests a strong prefetch for several reads,
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and corresponds to a prefetch function code of 20.
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</p>
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<p>‘<samp>#one_read_strong</samp>’ requests a strong prefetch for one read,
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and corresponds to a prefetch function code of 21.
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</p>
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<p>‘<samp>#n_writes_strong</samp>’ requests a strong prefetch for several writes,
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and corresponds to a prefetch function code of 22.
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</p>
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<p>‘<samp>#one_write_strong</samp>’ requests a strong prefetch for one write,
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and corresponds to a prefetch function code of 23.
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</p>
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<p>Onle one prefetch code may be specified. Here are some examples:
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</p>
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<div class="example">
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<pre class="example">prefetch [%l0 + %l2], #one_read
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prefetch [%g2 + 8], #n_writes
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prefetcha [%g1] 0x8, #unified
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prefetcha [%o0 + 0x10] %asi, #n_reads
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</pre></div>
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<p>The actual behavior of a given prefetch function code is processor
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specific. If a processor does not implement a given prefetch
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function code, it will treat the prefetch instruction as a nop.
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</p>
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<p>For instructions that accept an immediate address space identifier,
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<code>as</code> provides many mnemonics corresponding to
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V9 defined as well as UltraSPARC and Niagara extended values.
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For example, ‘<samp>#ASI_P</samp>’ and ‘<samp>#ASI_BLK_INIT_QUAD_LDD_AIUS</samp>’.
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See the V9 and processor specific manuals for details.
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</p>
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</li></ul>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Sparc_002dRelocs.html#Sparc_002dRelocs" accesskey="n" rel="next">Sparc-Relocs</a>, Previous: <a href="Sparc_002dRegs.html#Sparc_002dRegs" accesskey="p" rel="prev">Sparc-Regs</a>, Up: <a href="Sparc_002dSyntax.html#Sparc_002dSyntax" accesskey="u" rel="up">Sparc-Syntax</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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