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<a name="g_t80386-Dependent-Features"></a>
<h3 class="section">9.15 80386 Dependent Features</h3>
<a name="index-i386-support"></a>
<a name="index-i80386-support"></a>
<a name="index-x86_002d64-support"></a>
<p>The i386 version <code>as</code> supports both the original Intel 386
architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
extending the Intel architecture to 64-bits.
</p>
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<tr><td align="left" valign="top">&bull; <a href="i386_002dOptions.html#i386_002dOptions" accesskey="1">i386-Options</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Options
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<tr><td align="left" valign="top">&bull; <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="2">i386-Directives</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">X86 specific directives
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<tr><td align="left" valign="top">&bull; <a href="i386_002dSyntax.html#i386_002dSyntax" accesskey="3">i386-Syntax</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Syntactical considerations
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<tr><td align="left" valign="top">&bull; <a href="i386_002dMnemonics.html#i386_002dMnemonics" accesskey="4">i386-Mnemonics</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Instruction Naming
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<tr><td align="left" valign="top">&bull; <a href="i386_002dRegs.html#i386_002dRegs" accesskey="5">i386-Regs</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Register Naming
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<tr><td align="left" valign="top">&bull; <a href="i386_002dPrefixes.html#i386_002dPrefixes" accesskey="6">i386-Prefixes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Instruction Prefixes
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<tr><td align="left" valign="top">&bull; <a href="i386_002dMemory.html#i386_002dMemory" accesskey="7">i386-Memory</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Memory References
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<tr><td align="left" valign="top">&bull; <a href="i386_002dJumps.html#i386_002dJumps" accesskey="8">i386-Jumps</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Handling of Jump Instructions
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<tr><td align="left" valign="top">&bull; <a href="i386_002dFloat.html#i386_002dFloat" accesskey="9">i386-Float</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Floating Point
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<tr><td align="left" valign="top">&bull; <a href="i386_002dSIMD.html#i386_002dSIMD">i386-SIMD</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Intel&rsquo;s MMX and AMD&rsquo;s 3DNow! SIMD Operations
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<tr><td align="left" valign="top">&bull; <a href="i386_002dLWP.html#i386_002dLWP">i386-LWP</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AMD&rsquo;s Lightweight Profiling Instructions
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<tr><td align="left" valign="top">&bull; <a href="i386_002dBMI.html#i386_002dBMI">i386-BMI</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Bit Manipulation Instruction
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<tr><td align="left" valign="top">&bull; <a href="i386_002dTBM.html#i386_002dTBM">i386-TBM</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AMD&rsquo;s Trailing Bit Manipulation Instructions
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<tr><td align="left" valign="top">&bull; <a href="i386_002d16bit.html#i386_002d16bit">i386-16bit</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Writing 16-bit Code
</td></tr>
<tr><td align="left" valign="top">&bull; <a href="i386_002dArch.html#i386_002dArch">i386-Arch</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Specifying an x86 CPU architecture
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<tr><td align="left" valign="top">&bull; <a href="i386_002dBugs.html#i386_002dBugs">i386-Bugs</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">AT&amp;T Syntax bugs
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<tr><td align="left" valign="top">&bull; <a href="i386_002dNotes.html#i386_002dNotes">i386-Notes</a>:</td><td>&nbsp;&nbsp;</td><td align="left" valign="top">Notes
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