150 lines
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HTML
150 lines
12 KiB
HTML
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- This file documents the GNU Assembler "as".
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Copyright (C) 1991-2016 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled "GNU Free Documentation License".
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<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Using as: i386-Arch</title>
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<meta name="description" content="Using as: i386-Arch">
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<meta name="keywords" content="Using as: i386-Arch">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="i386_002dDependent.html#i386_002dDependent" rel="up" title="i386-Dependent">
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<link href="i386_002dBugs.html#i386_002dBugs" rel="next" title="i386-Bugs">
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<link href="i386_002d16bit.html#i386_002d16bit" rel="prev" title="i386-16bit">
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="i386_002dArch"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dBugs.html#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="i386_002d16bit.html#i386_002d16bit" accesskey="p" rel="prev">i386-16bit</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Specifying-CPU-Architecture"></a>
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<h4 class="subsection">9.15.15 Specifying CPU Architecture</h4>
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<a name="index-arch-directive_002c-i386"></a>
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<a name="index-i386-arch-directive"></a>
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<a name="index-arch-directive_002c-x86_002d64"></a>
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<a name="index-x86_002d64-arch-directive"></a>
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<p><code>as</code> may be told to assemble for a particular CPU
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(sub-)architecture with the <code>.arch <var>cpu_type</var></code> directive. This
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directive enables a warning when gas detects an instruction that is not
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supported on the CPU specified. The choices for <var>cpu_type</var> are:
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</p>
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<table>
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<tr><td width="20%">‘<samp>i8086</samp>’</td><td width="20%">‘<samp>i186</samp>’</td><td width="20%">‘<samp>i286</samp>’</td><td width="20%">‘<samp>i386</samp>’</td></tr>
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<tr><td width="20%">‘<samp>i486</samp>’</td><td width="20%">‘<samp>i586</samp>’</td><td width="20%">‘<samp>i686</samp>’</td><td width="20%">‘<samp>pentium</samp>’</td></tr>
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<tr><td width="20%">‘<samp>pentiumpro</samp>’</td><td width="20%">‘<samp>pentiumii</samp>’</td><td width="20%">‘<samp>pentiumiii</samp>’</td><td width="20%">‘<samp>pentium4</samp>’</td></tr>
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<tr><td width="20%">‘<samp>prescott</samp>’</td><td width="20%">‘<samp>nocona</samp>’</td><td width="20%">‘<samp>core</samp>’</td><td width="20%">‘<samp>core2</samp>’</td></tr>
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<tr><td width="20%">‘<samp>corei7</samp>’</td><td width="20%">‘<samp>l1om</samp>’</td><td width="20%">‘<samp>k1om</samp>’ ‘<samp>iamcu</samp>’</td></tr>
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<tr><td width="20%">‘<samp>k6</samp>’</td><td width="20%">‘<samp>k6_2</samp>’</td><td width="20%">‘<samp>athlon</samp>’</td><td width="20%">‘<samp>k8</samp>’</td></tr>
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<tr><td width="20%">‘<samp>amdfam10</samp>’</td><td width="20%">‘<samp>bdver1</samp>’</td><td width="20%">‘<samp>bdver2</samp>’</td><td width="20%">‘<samp>bdver3</samp>’</td></tr>
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<tr><td width="20%">‘<samp>bdver4</samp>’</td><td width="20%">‘<samp>znver1</samp>’</td><td width="20%">‘<samp>btver1</samp>’</td><td width="20%">‘<samp>btver2</samp>’</td></tr>
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<tr><td width="20%">‘<samp>generic32</samp>’</td><td width="20%">‘<samp>generic64</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.mmx</samp>’</td><td width="20%">‘<samp>.sse</samp>’</td><td width="20%">‘<samp>.sse2</samp>’</td><td width="20%">‘<samp>.sse3</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.ssse3</samp>’</td><td width="20%">‘<samp>.sse4.1</samp>’</td><td width="20%">‘<samp>.sse4.2</samp>’</td><td width="20%">‘<samp>.sse4</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.avx</samp>’</td><td width="20%">‘<samp>.vmx</samp>’</td><td width="20%">‘<samp>.smx</samp>’</td><td width="20%">‘<samp>.ept</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.clflush</samp>’</td><td width="20%">‘<samp>.movbe</samp>’</td><td width="20%">‘<samp>.xsave</samp>’</td><td width="20%">‘<samp>.xsaveopt</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.aes</samp>’</td><td width="20%">‘<samp>.pclmul</samp>’</td><td width="20%">‘<samp>.fma</samp>’</td><td width="20%">‘<samp>.fsgsbase</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.rdrnd</samp>’</td><td width="20%">‘<samp>.f16c</samp>’</td><td width="20%">‘<samp>.avx2</samp>’</td><td width="20%">‘<samp>.bmi2</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.lzcnt</samp>’</td><td width="20%">‘<samp>.invpcid</samp>’</td><td width="20%">‘<samp>.vmfunc</samp>’</td><td width="20%">‘<samp>.hle</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.rtm</samp>’</td><td width="20%">‘<samp>.adx</samp>’</td><td width="20%">‘<samp>.rdseed</samp>’</td><td width="20%">‘<samp>.prfchw</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.smap</samp>’</td><td width="20%">‘<samp>.mpx</samp>’</td><td width="20%">‘<samp>.sha</samp>’</td><td width="20%">‘<samp>.prefetchwt1</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.clflushopt</samp>’</td><td width="20%">‘<samp>.xsavec</samp>’</td><td width="20%">‘<samp>.xsaves</samp>’</td><td width="20%">‘<samp>.se1</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.avx512f</samp>’</td><td width="20%">‘<samp>.avx512cd</samp>’</td><td width="20%">‘<samp>.avx512er</samp>’</td><td width="20%">‘<samp>.avx512pf</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.avx512vl</samp>’</td><td width="20%">‘<samp>.avx512bw</samp>’</td><td width="20%">‘<samp>.avx512dq</samp>’</td><td width="20%">‘<samp>.avx512ifma</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.avx512vbmi</samp>’</td><td width="20%">‘<samp>.clwb</samp>’</td><td width="20%">‘<samp>.pcommit</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.3dnow</samp>’</td><td width="20%">‘<samp>.3dnowa</samp>’</td><td width="20%">‘<samp>.sse4a</samp>’</td><td width="20%">‘<samp>.sse5</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.syscall</samp>’</td><td width="20%">‘<samp>.rdtscp</samp>’</td><td width="20%">‘<samp>.svme</samp>’</td><td width="20%">‘<samp>.abm</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.lwp</samp>’</td><td width="20%">‘<samp>.fma4</samp>’</td><td width="20%">‘<samp>.xop</samp>’</td><td width="20%">‘<samp>.cx16</samp>’</td></tr>
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<tr><td width="20%">‘<samp>.padlock</samp>’</td><td width="20%">‘<samp>.clzero</samp>’</td><td width="20%">‘<samp>.mwaitx</samp>’</td><td width="20%">‘<samp>.rdpid</samp>’</td></tr>
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</table>
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<p>Apart from the warning, there are only two other effects on
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<code>as</code> operation; Firstly, if you specify a CPU other than
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‘<samp>i486</samp>’, then shift by one instructions such as ‘<samp>sarl $1, %eax</samp>’
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will automatically use a two byte opcode sequence. The larger three
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byte opcode sequence is used on the 486 (and when no architecture is
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specified) because it executes faster on the 486. Note that you can
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explicitly request the two byte opcode by writing ‘<samp>sarl %eax</samp>’.
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Secondly, if you specify ‘<samp>i8086</samp>’, ‘<samp>i186</samp>’, or ‘<samp>i286</samp>’,
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<em>and</em> ‘<samp>.code16</samp>’ or ‘<samp>.code16gcc</samp>’ then byte offset
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conditional jumps will be promoted when necessary to a two instruction
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sequence consisting of a conditional jump of the opposite sense around
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an unconditional jump to the target.
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</p>
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<p>Following the CPU architecture (but not a sub-architecture, which are those
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starting with a dot), you may specify ‘<samp>jumps</samp>’ or ‘<samp>nojumps</samp>’ to
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control automatic promotion of conditional jumps. ‘<samp>jumps</samp>’ is the
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default, and enables jump promotion; All external jumps will be of the long
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variety, and file-local jumps will be promoted as necessary.
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(see <a href="i386_002dJumps.html#i386_002dJumps">i386-Jumps</a>) ‘<samp>nojumps</samp>’ leaves external conditional jumps as
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byte offset jumps, and warns about file-local conditional jumps that
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<code>as</code> promotes.
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Unconditional jumps are treated as for ‘<samp>jumps</samp>’.
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</p>
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<p>For example
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</p>
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<div class="smallexample">
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<pre class="smallexample"> .arch i8086,nojumps
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</pre></div>
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<hr>
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<div class="header">
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<p>
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Next: <a href="i386_002dBugs.html#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="i386_002d16bit.html#i386_002d16bit" accesskey="p" rel="prev">i386-16bit</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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