151 lines
6.3 KiB
HTML
151 lines
6.3 KiB
HTML
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<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- This file documents the GNU Assembler "as".
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Copyright (C) 1991-2016 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled "GNU Free Documentation License".
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-->
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<!-- Created by GNU Texinfo 5.2, http://www.gnu.org/software/texinfo/ -->
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<head>
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<title>Using as: ARM Opcodes</title>
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<meta name="description" content="Using as: ARM Opcodes">
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<meta name="keywords" content="Using as: ARM Opcodes">
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<meta name="resource-type" content="document">
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<meta name="distribution" content="global">
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<meta name="Generator" content="makeinfo">
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link href="index.html#Top" rel="start" title="Top">
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="ARM_002dDependent.html#ARM_002dDependent" rel="up" title="ARM-Dependent">
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<link href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" rel="next" title="ARM Mapping Symbols">
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<link href="ARM-Directives.html#ARM-Directives" rel="prev" title="ARM Directives">
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<style type="text/css">
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-->
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</style>
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</head>
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="ARM-Opcodes"></a>
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<div class="header">
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<p>
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Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Opcodes-3"></a>
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<h4 class="subsection">9.4.5 Opcodes</h4>
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<a name="index-ARM-opcodes"></a>
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<a name="index-opcodes-for-ARM"></a>
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<p><code>as</code> implements all the standard ARM opcodes. It also
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implements several pseudo opcodes, including several synthetic load
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instructions.
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</p>
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<dl compact="compact">
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<dd>
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<a name="index-NOP-pseudo-op_002c-ARM"></a>
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</dd>
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<dt><code>NOP</code></dt>
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<dd><div class="smallexample">
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<pre class="smallexample"> nop
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</pre></div>
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<p>This pseudo op will always evaluate to a legal ARM instruction that does
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nothing. Currently it will evaluate to MOV r0, r0.
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</p>
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<a name="index-LDR-reg_002c_003d_003clabel_003e-pseudo-op_002c-ARM"></a>
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</dd>
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<dt><code>LDR</code></dt>
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<dd><div class="smallexample">
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<pre class="smallexample"> ldr <register> , = <expression>
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</pre></div>
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<p>If expression evaluates to a numeric constant then a MOV or MVN
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instruction will be used in place of the LDR instruction, if the
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constant can be generated by either of these instructions. Otherwise
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the constant will be placed into the nearest literal pool (if it not
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already there) and a PC relative LDR instruction will be generated.
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</p>
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<a name="index-ADR-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
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</dd>
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<dt><code>ADR</code></dt>
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<dd><div class="smallexample">
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<pre class="smallexample"> adr <register> <label>
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</pre></div>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to a PC relative ADD or SUB
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instruction depending upon where the label is located. If the label is
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out of range, or if it is not defined in the same file (and section) as
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the ADR instruction, then an error will be generated. This instruction
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will not make use of the literal pool.
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</p>
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<a name="index-ADRL-reg_002c_003clabel_003e-pseudo-op_002c-ARM"></a>
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</dd>
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<dt><code>ADRL</code></dt>
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<dd><div class="smallexample">
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<pre class="smallexample"> adrl <register> <label>
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</pre></div>
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<p>This instruction will load the address of <var>label</var> into the indicated
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register. The instruction will evaluate to one or two PC relative ADD
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or SUB instructions depending upon where the label is located. If a
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second instruction is not needed a NOP instruction will be generated in
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its place, so that this instruction is always 8 bytes long.
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</p>
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<p>If the label is out of range, or if it is not defined in the same file
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(and section) as the ADRL instruction, then an error will be generated.
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This instruction will not make use of the literal pool.
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</p>
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</dd>
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</dl>
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<p>For information on the ARM or Thumb instruction sets, see <cite>ARM
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Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines
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Ltd.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="ARM-Mapping-Symbols.html#ARM-Mapping-Symbols" accesskey="n" rel="next">ARM Mapping Symbols</a>, Previous: <a href="ARM-Directives.html#ARM-Directives" accesskey="p" rel="prev">ARM Directives</a>, Up: <a href="ARM_002dDependent.html#ARM_002dDependent" accesskey="u" rel="up">ARM-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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</body>
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</html>
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