779 lines
20 KiB
C
779 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// tegra210_mvc.c - Tegra210 MVC driver
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//
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// Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra210_mvc.h"
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#include "tegra_cif.h"
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static const struct reg_default tegra210_mvc_reg_defaults[] = {
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{ TEGRA210_MVC_RX_INT_MASK, 0x00000001},
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{ TEGRA210_MVC_RX_CIF_CTRL, 0x00007700},
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{ TEGRA210_MVC_TX_INT_MASK, 0x00000001},
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{ TEGRA210_MVC_TX_CIF_CTRL, 0x00007700},
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{ TEGRA210_MVC_CG, 0x1},
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{ TEGRA210_MVC_CTRL, TEGRA210_MVC_CTRL_DEFAULT},
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{ TEGRA210_MVC_INIT_VOL, 0x00800000},
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{ TEGRA210_MVC_TARGET_VOL, 0x00800000},
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{ TEGRA210_MVC_DURATION, 0x000012c0},
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{ TEGRA210_MVC_DURATION_INV, 0x0006d3a0},
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{ TEGRA210_MVC_POLY_N1, 0x0000007d},
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{ TEGRA210_MVC_POLY_N2, 0x00000271},
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{ TEGRA210_MVC_PEAK_CTRL, 0x000012c0},
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{ TEGRA210_MVC_CFG_RAM_CTRL, 0x00004000},
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};
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static const struct tegra210_mvc_gain_params gain_params = {
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.poly_coeff = { 23738319, 659403, -3680,
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15546680, 2530732, -120985,
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12048422, 5527252, -785042 },
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.poly_n1 = 16,
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.poly_n2 = 63,
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.duration = 150,
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.duration_inv = 14316558,
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};
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static int __maybe_unused tegra210_mvc_runtime_suspend(struct device *dev)
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{
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struct tegra210_mvc *mvc = dev_get_drvdata(dev);
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regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &(mvc->ctrl_value));
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regcache_cache_only(mvc->regmap, true);
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regcache_mark_dirty(mvc->regmap);
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return 0;
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}
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static int __maybe_unused tegra210_mvc_runtime_resume(struct device *dev)
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{
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struct tegra210_mvc *mvc = dev_get_drvdata(dev);
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regcache_cache_only(mvc->regmap, false);
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regcache_sync(mvc->regmap);
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regmap_write(mvc->regmap, TEGRA210_MVC_CTRL, mvc->ctrl_value);
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regmap_update_bits(mvc->regmap,
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TEGRA210_MVC_SWITCH,
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TEGRA210_MVC_VOLUME_SWITCH_MASK,
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TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
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return 0;
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}
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static void tegra210_mvc_write_ram(struct regmap *regmap)
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{
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int i;
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regmap_write(regmap, TEGRA210_MVC_CFG_RAM_CTRL,
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TEGRA210_MVC_CFG_RAM_CTRL_SEQ_ACCESS_EN |
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TEGRA210_MVC_CFG_RAM_CTRL_ADDR_INIT_EN |
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TEGRA210_MVC_CFG_RAM_CTRL_RW_WRITE);
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for (i = 0; i < NUM_GAIN_POLY_COEFFS; i++)
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regmap_write(regmap, TEGRA210_MVC_CFG_RAM_DATA,
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gain_params.poly_coeff[i]);
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}
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static void tegra210_mvc_conv_vol(struct tegra210_mvc *mvc, u8 chan, s32 val)
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{
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/*
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* Volume control read from mixer control is with
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* 100x scaling; for CURVE_POLY the reg range
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* is 0-100 (linear, Q24) and for CURVE_LINEAR
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* it is -120dB to +40dB (Q8)
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*/
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if (mvc->curve_type == CURVE_POLY) {
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if (val > 10000)
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val = 10000;
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mvc->volume[chan] = ((val * (1<<8)) / 100) << 16;
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} else {
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val -= 12000;
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mvc->volume[chan] = (val * (1<<8)) / 100;
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}
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}
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static u32 tegra210_mvc_get_ctrl_reg(struct snd_kcontrol *kcontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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u32 val;
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pm_runtime_get_sync(cmpnt->dev);
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regmap_read(mvc->regmap, TEGRA210_MVC_CTRL, &val);
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pm_runtime_put(cmpnt->dev);
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return val;
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}
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static int tegra210_mvc_get_mute(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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u32 val = tegra210_mvc_get_ctrl_reg(kcontrol);
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u8 mute_mask = TEGRA210_GET_MUTE_VAL(val);
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/*
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* If per channel control is enabled, then return
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* exact mute/unmute setting of all channels.
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*
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* Else report setting based on CH0 bit to reflect
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* the correct HW state.
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*/
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if (val & TEGRA210_MVC_PER_CHAN_CTRL_EN) {
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ucontrol->value.integer.value[0] = mute_mask;
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} else {
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if (mute_mask & TEGRA210_MVC_CH0_MUTE_EN)
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ucontrol->value.integer.value[0] =
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TEGRA210_MUTE_MASK_EN;
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else
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ucontrol->value.integer.value[0] = 0;
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}
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return 0;
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}
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static int tegra210_mvc_get_master_mute(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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u32 val = tegra210_mvc_get_ctrl_reg(kcontrol);
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u8 mute_mask = TEGRA210_GET_MUTE_VAL(val);
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/*
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* If per channel control is disabled, then return
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* master mute/unmute setting based on CH0 bit.
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*
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* Else report settings based on state of all
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* channels.
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*/
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if (!(val & TEGRA210_MVC_PER_CHAN_CTRL_EN)) {
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ucontrol->value.integer.value[0] =
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mute_mask & TEGRA210_MVC_CH0_MUTE_EN;
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} else {
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if (mute_mask == TEGRA210_MUTE_MASK_EN)
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ucontrol->value.integer.value[0] =
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TEGRA210_MVC_CH0_MUTE_EN;
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else
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ucontrol->value.integer.value[0] = 0;
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}
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return 0;
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}
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static int tegra210_mvc_volume_switch_timeout(struct snd_soc_component *cmpnt)
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{
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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u32 value;
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int err;
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err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SWITCH,
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value, !(value & TEGRA210_MVC_VOLUME_SWITCH_MASK),
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10, 10000);
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if (err < 0)
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dev_err(cmpnt->dev,
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"Volume switch trigger is still active, err = %d\n",
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err);
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return err;
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}
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static int tegra210_mvc_update_mute(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol,
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bool per_chan_ctrl)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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u32 mute_val = ucontrol->value.integer.value[0];
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u32 per_ch_ctrl_val;
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bool change = false;
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int err;
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pm_runtime_get_sync(cmpnt->dev);
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err = tegra210_mvc_volume_switch_timeout(cmpnt);
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if (err < 0)
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goto end;
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if (per_chan_ctrl) {
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per_ch_ctrl_val = TEGRA210_MVC_PER_CHAN_CTRL_EN;
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} else {
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per_ch_ctrl_val = 0;
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if (mute_val)
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mute_val = TEGRA210_MUTE_MASK_EN;
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}
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regmap_update_bits_check(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_MUTE_MASK,
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mute_val << TEGRA210_MVC_MUTE_SHIFT,
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&change);
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if (change) {
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK,
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per_ch_ctrl_val);
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
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TEGRA210_MVC_VOLUME_SWITCH_MASK,
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TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
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}
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end:
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pm_runtime_put(cmpnt->dev);
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if (err < 0)
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return err;
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if (change)
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return 1;
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return 0;
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}
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static int tegra210_mvc_put_mute(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return tegra210_mvc_update_mute(kcontrol, ucontrol, true);
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}
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static int tegra210_mvc_put_master_mute(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return tegra210_mvc_update_mute(kcontrol, ucontrol, false);
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}
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static int tegra210_mvc_get_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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u8 chan = TEGRA210_MVC_GET_CHAN(mc->reg, TEGRA210_MVC_TARGET_VOL);
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s32 val = mvc->volume[chan];
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if (mvc->curve_type == CURVE_POLY) {
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val = ((val >> 16) * 100) >> 8;
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} else {
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val = (val * 100) >> 8;
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val += 12000;
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}
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ucontrol->value.integer.value[0] = val;
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return 0;
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}
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static int tegra210_mvc_get_master_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return tegra210_mvc_get_vol(kcontrol, ucontrol);
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}
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static int tegra210_mvc_update_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol,
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bool per_ch_enable)
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{
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struct soc_mixer_control *mc =
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(struct soc_mixer_control *)kcontrol->private_value;
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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u8 chan = TEGRA210_MVC_GET_CHAN(mc->reg, TEGRA210_MVC_TARGET_VOL);
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int old_volume = mvc->volume[chan];
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int err, i;
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pm_runtime_get_sync(cmpnt->dev);
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err = tegra210_mvc_volume_switch_timeout(cmpnt);
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if (err < 0)
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goto end;
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tegra210_mvc_conv_vol(mvc, chan, ucontrol->value.integer.value[0]);
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if (mvc->volume[chan] == old_volume) {
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err = 0;
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goto end;
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}
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if (per_ch_enable) {
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK,
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TEGRA210_MVC_PER_CHAN_CTRL_EN);
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} else {
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_PER_CHAN_CTRL_EN_MASK, 0);
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for (i = 1; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
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mvc->volume[i] = mvc->volume[chan];
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}
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/* Configure init volume same as target volume */
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regmap_write(mvc->regmap,
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TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_INIT_VOL, chan),
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mvc->volume[chan]);
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regmap_write(mvc->regmap, mc->reg, mvc->volume[chan]);
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
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TEGRA210_MVC_VOLUME_SWITCH_MASK,
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TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
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err = 1;
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end:
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pm_runtime_put(cmpnt->dev);
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return err;
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}
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static int tegra210_mvc_put_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return tegra210_mvc_update_vol(kcontrol, ucontrol, true);
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}
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static int tegra210_mvc_put_master_vol(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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return tegra210_mvc_update_vol(kcontrol, ucontrol, false);
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}
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static void tegra210_mvc_reset_vol_settings(struct tegra210_mvc *mvc,
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struct device *dev)
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{
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int i;
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/* Change volume to default init for new curve type */
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if (mvc->curve_type == CURVE_POLY) {
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for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
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mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_POLY;
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} else {
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for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++)
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mvc->volume[i] = TEGRA210_MVC_INIT_VOL_DEFAULT_LINEAR;
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}
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pm_runtime_get_sync(dev);
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/* Program curve type */
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_CTRL,
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TEGRA210_MVC_CURVE_TYPE_MASK,
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mvc->curve_type <<
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TEGRA210_MVC_CURVE_TYPE_SHIFT);
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/* Init volume for all channels */
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for (i = 0; i < TEGRA210_MVC_MAX_CHAN_COUNT; i++) {
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regmap_write(mvc->regmap,
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TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_INIT_VOL, i),
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mvc->volume[i]);
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regmap_write(mvc->regmap,
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TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_TARGET_VOL, i),
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mvc->volume[i]);
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}
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/* Trigger volume switch */
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regmap_update_bits(mvc->regmap, TEGRA210_MVC_SWITCH,
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TEGRA210_MVC_VOLUME_SWITCH_MASK,
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TEGRA210_MVC_VOLUME_SWITCH_TRIGGER);
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pm_runtime_put(dev);
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}
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static int tegra210_mvc_get_curve_type(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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ucontrol->value.enumerated.item[0] = mvc->curve_type;
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return 0;
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}
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static int tegra210_mvc_put_curve_type(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
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struct tegra210_mvc *mvc = snd_soc_component_get_drvdata(cmpnt);
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unsigned int value;
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regmap_read(mvc->regmap, TEGRA210_MVC_ENABLE, &value);
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if (value & TEGRA210_MVC_EN) {
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dev_err(cmpnt->dev,
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"Curve type can't be set when MVC is running\n");
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return -EINVAL;
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}
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if (mvc->curve_type == ucontrol->value.enumerated.item[0])
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return 0;
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mvc->curve_type = ucontrol->value.enumerated.item[0];
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tegra210_mvc_reset_vol_settings(mvc, cmpnt->dev);
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return 1;
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}
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static int tegra210_mvc_set_audio_cif(struct tegra210_mvc *mvc,
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struct snd_pcm_hw_params *params,
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unsigned int reg)
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{
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unsigned int channels, audio_bits;
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struct tegra_cif_conf cif_conf;
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memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
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channels = params_channels(params);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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audio_bits = TEGRA_ACIF_BITS_16;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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audio_bits = TEGRA_ACIF_BITS_32;
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break;
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default:
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return -EINVAL;
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}
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cif_conf.audio_ch = channels;
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cif_conf.client_ch = channels;
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cif_conf.audio_bits = audio_bits;
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cif_conf.client_bits = audio_bits;
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tegra_set_cif(mvc->regmap, reg, &cif_conf);
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return 0;
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}
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static int tegra210_mvc_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->dev;
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struct tegra210_mvc *mvc = snd_soc_dai_get_drvdata(dai);
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int err, val;
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/*
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* Soft Reset: Below performs module soft reset which clears
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* all FSM logic, flushes flow control of FIFO and resets the
|
|
* state register. It also brings module back to disabled
|
|
* state (without flushing the data in the pipe).
|
|
*/
|
|
regmap_write(mvc->regmap, TEGRA210_MVC_SOFT_RESET, 1);
|
|
|
|
err = regmap_read_poll_timeout(mvc->regmap, TEGRA210_MVC_SOFT_RESET,
|
|
val, !val, 10, 10000);
|
|
if (err < 0) {
|
|
dev_err(dev, "SW reset failed, err = %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* Set RX CIF */
|
|
err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_RX_CIF_CTRL);
|
|
if (err) {
|
|
dev_err(dev, "Can't set MVC RX CIF: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
/* Set TX CIF */
|
|
err = tegra210_mvc_set_audio_cif(mvc, params, TEGRA210_MVC_TX_CIF_CTRL);
|
|
if (err) {
|
|
dev_err(dev, "Can't set MVC TX CIF: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
tegra210_mvc_write_ram(mvc->regmap);
|
|
|
|
/* Program poly_n1, poly_n2, duration */
|
|
regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N1, gain_params.poly_n1);
|
|
regmap_write(mvc->regmap, TEGRA210_MVC_POLY_N2, gain_params.poly_n2);
|
|
regmap_write(mvc->regmap, TEGRA210_MVC_DURATION, gain_params.duration);
|
|
|
|
/* Program duration_inv */
|
|
regmap_write(mvc->regmap, TEGRA210_MVC_DURATION_INV,
|
|
gain_params.duration_inv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops tegra210_mvc_dai_ops = {
|
|
.hw_params = tegra210_mvc_hw_params,
|
|
};
|
|
|
|
static const char * const tegra210_mvc_curve_type_text[] = {
|
|
"Poly",
|
|
"Linear",
|
|
};
|
|
|
|
static const struct soc_enum tegra210_mvc_curve_type_ctrl =
|
|
SOC_ENUM_SINGLE_EXT(2, tegra210_mvc_curve_type_text);
|
|
|
|
#define TEGRA210_MVC_VOL_CTRL(chan) \
|
|
SOC_SINGLE_EXT("Channel" #chan " Volume", \
|
|
TEGRA210_MVC_REG_OFFSET(TEGRA210_MVC_TARGET_VOL, \
|
|
(chan - 1)), \
|
|
0, 16000, 0, tegra210_mvc_get_vol, \
|
|
tegra210_mvc_put_vol)
|
|
|
|
static const struct snd_kcontrol_new tegra210_mvc_vol_ctrl[] = {
|
|
/* Per channel volume control */
|
|
TEGRA210_MVC_VOL_CTRL(1),
|
|
TEGRA210_MVC_VOL_CTRL(2),
|
|
TEGRA210_MVC_VOL_CTRL(3),
|
|
TEGRA210_MVC_VOL_CTRL(4),
|
|
TEGRA210_MVC_VOL_CTRL(5),
|
|
TEGRA210_MVC_VOL_CTRL(6),
|
|
TEGRA210_MVC_VOL_CTRL(7),
|
|
TEGRA210_MVC_VOL_CTRL(8),
|
|
|
|
/* Per channel mute */
|
|
SOC_SINGLE_EXT("Per Chan Mute Mask",
|
|
TEGRA210_MVC_CTRL, 0, TEGRA210_MUTE_MASK_EN, 0,
|
|
tegra210_mvc_get_mute, tegra210_mvc_put_mute),
|
|
|
|
/* Master volume */
|
|
SOC_SINGLE_EXT("Volume", TEGRA210_MVC_TARGET_VOL, 0, 16000, 0,
|
|
tegra210_mvc_get_master_vol,
|
|
tegra210_mvc_put_master_vol),
|
|
|
|
/* Master mute */
|
|
SOC_SINGLE_EXT("Mute", TEGRA210_MVC_CTRL, 0, 1, 0,
|
|
tegra210_mvc_get_master_mute,
|
|
tegra210_mvc_put_master_mute),
|
|
|
|
SOC_ENUM_EXT("Curve Type", tegra210_mvc_curve_type_ctrl,
|
|
tegra210_mvc_get_curve_type, tegra210_mvc_put_curve_type),
|
|
};
|
|
|
|
static struct snd_soc_dai_driver tegra210_mvc_dais[] = {
|
|
/* Input */
|
|
{
|
|
.name = "MVC-RX-CIF",
|
|
.playback = {
|
|
.stream_name = "RX-CIF-Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
.rates = SNDRV_PCM_RATE_8000_192000,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.capture = {
|
|
.stream_name = "RX-CIF-Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
.rates = SNDRV_PCM_RATE_8000_192000,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
},
|
|
|
|
/* Output */
|
|
{
|
|
.name = "MVC-TX-CIF",
|
|
.playback = {
|
|
.stream_name = "TX-CIF-Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
.rates = SNDRV_PCM_RATE_8000_192000,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.capture = {
|
|
.stream_name = "TX-CIF-Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 8,
|
|
.rates = SNDRV_PCM_RATE_8000_192000,
|
|
.formats = SNDRV_PCM_FMTBIT_S8 |
|
|
SNDRV_PCM_FMTBIT_S16_LE |
|
|
SNDRV_PCM_FMTBIT_S32_LE,
|
|
},
|
|
.ops = &tegra210_mvc_dai_ops,
|
|
}
|
|
};
|
|
|
|
static const struct snd_soc_dapm_widget tegra210_mvc_widgets[] = {
|
|
SND_SOC_DAPM_AIF_IN("RX", NULL, 0, SND_SOC_NOPM, 0, 0),
|
|
SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_MVC_ENABLE,
|
|
TEGRA210_MVC_EN_SHIFT, 0),
|
|
};
|
|
|
|
#define MVC_ROUTES(sname) \
|
|
{ "RX XBAR-" sname, NULL, "XBAR-TX" }, \
|
|
{ "RX-CIF-" sname, NULL, "RX XBAR-" sname }, \
|
|
{ "RX", NULL, "RX-CIF-" sname }, \
|
|
{ "TX-CIF-" sname, NULL, "TX" }, \
|
|
{ "TX XBAR-" sname, NULL, "TX-CIF-" sname }, \
|
|
{ "XBAR-RX", NULL, "TX XBAR-" sname }
|
|
|
|
static const struct snd_soc_dapm_route tegra210_mvc_routes[] = {
|
|
{ "TX", NULL, "RX" },
|
|
MVC_ROUTES("Playback"),
|
|
MVC_ROUTES("Capture"),
|
|
};
|
|
|
|
static const struct snd_soc_component_driver tegra210_mvc_cmpnt = {
|
|
.dapm_widgets = tegra210_mvc_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(tegra210_mvc_widgets),
|
|
.dapm_routes = tegra210_mvc_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(tegra210_mvc_routes),
|
|
.controls = tegra210_mvc_vol_ctrl,
|
|
.num_controls = ARRAY_SIZE(tegra210_mvc_vol_ctrl),
|
|
};
|
|
|
|
static bool tegra210_mvc_rd_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_MVC_RX_STATUS ... TEGRA210_MVC_CONFIG_ERR_TYPE:
|
|
return true;
|
|
default:
|
|
return false;
|
|
};
|
|
}
|
|
|
|
static bool tegra210_mvc_wr_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_MVC_RX_INT_MASK ... TEGRA210_MVC_RX_CIF_CTRL:
|
|
case TEGRA210_MVC_TX_INT_MASK ... TEGRA210_MVC_TX_CIF_CTRL:
|
|
case TEGRA210_MVC_ENABLE ... TEGRA210_MVC_CG:
|
|
case TEGRA210_MVC_CTRL ... TEGRA210_MVC_CFG_RAM_DATA:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool tegra210_mvc_volatile_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case TEGRA210_MVC_RX_STATUS:
|
|
case TEGRA210_MVC_RX_INT_STATUS:
|
|
case TEGRA210_MVC_RX_INT_SET:
|
|
|
|
case TEGRA210_MVC_TX_STATUS:
|
|
case TEGRA210_MVC_TX_INT_STATUS:
|
|
case TEGRA210_MVC_TX_INT_SET:
|
|
|
|
case TEGRA210_MVC_SOFT_RESET:
|
|
case TEGRA210_MVC_STATUS:
|
|
case TEGRA210_MVC_INT_STATUS:
|
|
case TEGRA210_MVC_SWITCH:
|
|
case TEGRA210_MVC_CFG_RAM_CTRL:
|
|
case TEGRA210_MVC_CFG_RAM_DATA:
|
|
case TEGRA210_MVC_PEAK_VALUE:
|
|
case TEGRA210_MVC_CTRL:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static const struct regmap_config tegra210_mvc_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = TEGRA210_MVC_CONFIG_ERR_TYPE,
|
|
.writeable_reg = tegra210_mvc_wr_reg,
|
|
.readable_reg = tegra210_mvc_rd_reg,
|
|
.volatile_reg = tegra210_mvc_volatile_reg,
|
|
.reg_defaults = tegra210_mvc_reg_defaults,
|
|
.num_reg_defaults = ARRAY_SIZE(tegra210_mvc_reg_defaults),
|
|
.cache_type = REGCACHE_FLAT,
|
|
};
|
|
|
|
static const struct of_device_id tegra210_mvc_of_match[] = {
|
|
{ .compatible = "nvidia,tegra210-mvc" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tegra210_mvc_of_match);
|
|
|
|
static int tegra210_mvc_platform_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct tegra210_mvc *mvc;
|
|
void __iomem *regs;
|
|
int err;
|
|
|
|
mvc = devm_kzalloc(dev, sizeof(*mvc), GFP_KERNEL);
|
|
if (!mvc)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, mvc);
|
|
|
|
mvc->curve_type = CURVE_LINEAR;
|
|
mvc->ctrl_value = TEGRA210_MVC_CTRL_DEFAULT;
|
|
|
|
regs = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
mvc->regmap = devm_regmap_init_mmio(dev, regs,
|
|
&tegra210_mvc_regmap_config);
|
|
if (IS_ERR(mvc->regmap)) {
|
|
dev_err(dev, "regmap init failed\n");
|
|
return PTR_ERR(mvc->regmap);
|
|
}
|
|
|
|
regcache_cache_only(mvc->regmap, true);
|
|
|
|
err = devm_snd_soc_register_component(dev, &tegra210_mvc_cmpnt,
|
|
tegra210_mvc_dais,
|
|
ARRAY_SIZE(tegra210_mvc_dais));
|
|
if (err) {
|
|
dev_err(dev, "can't register MVC component, err: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
tegra210_mvc_reset_vol_settings(mvc, &pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra210_mvc_platform_remove(struct platform_device *pdev)
|
|
{
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops tegra210_mvc_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra210_mvc_runtime_suspend,
|
|
tegra210_mvc_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
};
|
|
|
|
static struct platform_driver tegra210_mvc_driver = {
|
|
.driver = {
|
|
.name = "tegra210-mvc",
|
|
.of_match_table = tegra210_mvc_of_match,
|
|
.pm = &tegra210_mvc_pm_ops,
|
|
},
|
|
.probe = tegra210_mvc_platform_probe,
|
|
.remove = tegra210_mvc_platform_remove,
|
|
};
|
|
module_platform_driver(tegra210_mvc_driver)
|
|
|
|
MODULE_AUTHOR("Arun Shamanna Lakshmi <aruns@nvidia.com>");
|
|
MODULE_DESCRIPTION("Tegra210 MVC ASoC driver");
|
|
MODULE_LICENSE("GPL v2");
|