121 lines
3.9 KiB
C
121 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra20_das.h - Definitions for Tegra20 DAS driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010,2012 - NVIDIA, Inc.
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*/
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#ifndef __TEGRA20_DAS_H__
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#define __TEGRA20_DAS_H__
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/* Register TEGRA20_DAS_DAP_CTRL_SEL */
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#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
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#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
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#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
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/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
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#define TEGRA20_DAS_DAP_SEL_DAC1 0
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#define TEGRA20_DAS_DAP_SEL_DAC2 1
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#define TEGRA20_DAS_DAP_SEL_DAC3 2
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#define TEGRA20_DAS_DAP_SEL_DAP1 16
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#define TEGRA20_DAS_DAP_SEL_DAP2 17
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#define TEGRA20_DAS_DAP_SEL_DAP3 18
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#define TEGRA20_DAS_DAP_SEL_DAP4 19
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#define TEGRA20_DAS_DAP_SEL_DAP5 20
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/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
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/*
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* Values for:
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
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*/
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#define TEGRA20_DAS_DAC_SEL_DAP1 0
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#define TEGRA20_DAS_DAC_SEL_DAP2 1
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#define TEGRA20_DAS_DAC_SEL_DAP3 2
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#define TEGRA20_DAS_DAC_SEL_DAP4 3
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#define TEGRA20_DAS_DAC_SEL_DAP5 4
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/*
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* Names/IDs of the DACs/DAPs.
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*/
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#define TEGRA20_DAS_DAP_ID_1 0
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#define TEGRA20_DAS_DAP_ID_2 1
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#define TEGRA20_DAS_DAP_ID_3 2
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#define TEGRA20_DAS_DAP_ID_4 3
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#define TEGRA20_DAS_DAP_ID_5 4
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#define TEGRA20_DAS_DAC_ID_1 0
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#define TEGRA20_DAS_DAC_ID_2 1
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#define TEGRA20_DAS_DAC_ID_3 2
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struct tegra20_das {
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struct device *dev;
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struct regmap *regmap;
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};
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/*
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* Terminology:
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* DAS: Digital audio switch (HW module controlled by this driver)
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* DAP: Digital audio port (port/pins on Tegra device)
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* DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
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*
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* The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
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* DAC, or another DAP. When DAPs are connected, one must be the master and
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* one the slave. Each DAC allows selection of a specific DAP for input, to
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* cater for the case where N DAPs are connected to 1 DAC for broadcast
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* output.
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*
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* This driver is dumb; no attempt is made to ensure that a valid routing
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* configuration is programmed.
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*/
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/*
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* Connect a DAP to a DAC
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* dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
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* dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
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*/
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extern int tegra20_das_connect_dap_to_dac(int dap, int dac);
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/*
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* Connect a DAP to another DAP
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* dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
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* other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
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* master: Is this DAP the master (1) or slave (0)
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* sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
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* sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
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*/
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extern int tegra20_das_connect_dap_to_dap(int dap, int otherdap,
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int master, int sdata1rx,
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int sdata2rx);
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/*
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* Connect a DAC's input to a DAP
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* (DAC outputs are selected by the DAP)
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* dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
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* dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
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*/
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extern int tegra20_das_connect_dac_to_dap(int dac, int dap);
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#endif
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