118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
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#ifndef DT_BINDINGS_AST2600_CLOCK_H
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#define DT_BINDINGS_AST2600_CLOCK_H
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#define ASPEED_CLK_GATE_ECLK 0
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#define ASPEED_CLK_GATE_GCLK 1
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#define ASPEED_CLK_GATE_MCLK 2
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#define ASPEED_CLK_GATE_VCLK 3
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#define ASPEED_CLK_GATE_BCLK 4
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#define ASPEED_CLK_GATE_DCLK 5
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#define ASPEED_CLK_GATE_LCLK 6
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#define ASPEED_CLK_GATE_LHCCLK 7
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#define ASPEED_CLK_GATE_D1CLK 8
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#define ASPEED_CLK_GATE_YCLK 9
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#define ASPEED_CLK_GATE_REF0CLK 10
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#define ASPEED_CLK_GATE_REF1CLK 11
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#define ASPEED_CLK_GATE_ESPICLK 12
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#define ASPEED_CLK_GATE_USBUHCICLK 13
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#define ASPEED_CLK_GATE_USBPORT1CLK 14
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#define ASPEED_CLK_GATE_USBPORT2CLK 15
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#define ASPEED_CLK_GATE_RSACLK 16
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#define ASPEED_CLK_GATE_RVASCLK 17
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#define ASPEED_CLK_GATE_MAC1CLK 18
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#define ASPEED_CLK_GATE_MAC2CLK 19
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#define ASPEED_CLK_GATE_MAC3CLK 20
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#define ASPEED_CLK_GATE_MAC4CLK 21
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#define ASPEED_CLK_GATE_UART1CLK 22
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#define ASPEED_CLK_GATE_UART2CLK 23
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#define ASPEED_CLK_GATE_UART3CLK 24
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#define ASPEED_CLK_GATE_UART4CLK 25
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#define ASPEED_CLK_GATE_UART5CLK 26
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#define ASPEED_CLK_GATE_UART6CLK 27
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#define ASPEED_CLK_GATE_UART7CLK 28
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#define ASPEED_CLK_GATE_UART8CLK 29
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#define ASPEED_CLK_GATE_UART9CLK 30
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#define ASPEED_CLK_GATE_UART10CLK 31
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#define ASPEED_CLK_GATE_UART11CLK 32
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#define ASPEED_CLK_GATE_UART12CLK 33
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#define ASPEED_CLK_GATE_UART13CLK 34
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#define ASPEED_CLK_GATE_SDCLK 35
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#define ASPEED_CLK_GATE_EMMCCLK 36
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#define ASPEED_CLK_GATE_I3C0CLK 37
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#define ASPEED_CLK_GATE_I3C1CLK 38
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#define ASPEED_CLK_GATE_I3C2CLK 39
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#define ASPEED_CLK_GATE_I3C3CLK 40
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#define ASPEED_CLK_GATE_I3C4CLK 41
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#define ASPEED_CLK_GATE_I3C5CLK 42
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#define ASPEED_CLK_GATE_I3C6CLK 43
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#define ASPEED_CLK_GATE_I3C7CLK 44
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#define ASPEED_CLK_GATE_FSICLK 45
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#define ASPEED_CLK_HPLL 46
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#define ASPEED_CLK_MPLL 47
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#define ASPEED_CLK_DPLL 48
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#define ASPEED_CLK_EPLL 49
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#define ASPEED_CLK_APLL 50
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#define ASPEED_CLK_AHB 51
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#define ASPEED_CLK_APB1 52
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#define ASPEED_CLK_APB2 53
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#define ASPEED_CLK_BCLK 54
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#define ASPEED_CLK_D1CLK 55
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#define ASPEED_CLK_VCLK 56
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#define ASPEED_CLK_LHCLK 57
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#define ASPEED_CLK_UART 58
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#define ASPEED_CLK_UARTX 59
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#define ASPEED_CLK_SDIO 60
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#define ASPEED_CLK_EMMC 61
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#define ASPEED_CLK_ECLK 62
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#define ASPEED_CLK_ECLK_MUX 63
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#define ASPEED_CLK_MAC12 64
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#define ASPEED_CLK_MAC34 65
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#define ASPEED_CLK_USBPHY_40M 66
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#define ASPEED_CLK_MAC1RCLK 67
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#define ASPEED_CLK_MAC2RCLK 68
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#define ASPEED_CLK_MAC3RCLK 69
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#define ASPEED_CLK_MAC4RCLK 70
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/* Only list resets here that are not part of a gate */
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#define ASPEED_RESET_ADC 55
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#define ASPEED_RESET_JTAG_MASTER2 54
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#define ASPEED_RESET_I3C_DMA 39
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#define ASPEED_RESET_PWM 37
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#define ASPEED_RESET_PECI 36
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#define ASPEED_RESET_MII 35
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#define ASPEED_RESET_I2C 34
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#define ASPEED_RESET_H2X 31
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#define ASPEED_RESET_GP_MCU 30
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#define ASPEED_RESET_DP_MCU 29
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#define ASPEED_RESET_DP 28
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#define ASPEED_RESET_RC_XDMA 27
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#define ASPEED_RESET_GRAPHICS 26
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#define ASPEED_RESET_DEV_XDMA 25
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#define ASPEED_RESET_DEV_MCTP 24
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#define ASPEED_RESET_RC_MCTP 23
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#define ASPEED_RESET_JTAG_MASTER 22
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#define ASPEED_RESET_PCIE_DEV_O 21
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#define ASPEED_RESET_PCIE_DEV_OEN 20
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#define ASPEED_RESET_PCIE_RC_O 19
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#define ASPEED_RESET_PCIE_RC_OEN 18
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#define ASPEED_RESET_PCI_DP 5
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#define ASPEED_RESET_AHB 1
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#define ASPEED_RESET_SDRAM 0
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#endif
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