297 lines
6.8 KiB
C
297 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Backend - Handles the virtual fields found on the capability lists
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* in the configuration space.
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*
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* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include "pciback.h"
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#include "conf_space.h"
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static LIST_HEAD(capabilities);
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struct xen_pcibk_config_capability {
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struct list_head cap_list;
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int capability;
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/* If the device has the capability found above, add these fields */
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const struct config_field *fields;
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};
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static const struct config_field caplist_header[] = {
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{
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.offset = PCI_CAP_LIST_ID,
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.size = 2, /* encompass PCI_CAP_LIST_ID & PCI_CAP_LIST_NEXT */
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.u.w.read = xen_pcibk_read_config_word,
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.u.w.write = NULL,
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},
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{}
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};
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static inline void register_capability(struct xen_pcibk_config_capability *cap)
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{
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list_add_tail(&cap->cap_list, &capabilities);
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}
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int xen_pcibk_config_capability_add_fields(struct pci_dev *dev)
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{
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int err = 0;
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struct xen_pcibk_config_capability *cap;
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int cap_offset;
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list_for_each_entry(cap, &capabilities, cap_list) {
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cap_offset = pci_find_capability(dev, cap->capability);
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if (cap_offset) {
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dev_dbg(&dev->dev, "Found capability 0x%x at 0x%x\n",
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cap->capability, cap_offset);
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err = xen_pcibk_config_add_fields_offset(dev,
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caplist_header,
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cap_offset);
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if (err)
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goto out;
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err = xen_pcibk_config_add_fields_offset(dev,
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cap->fields,
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cap_offset);
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if (err)
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goto out;
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}
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}
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out:
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return err;
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}
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static int vpd_address_write(struct pci_dev *dev, int offset, u16 value,
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void *data)
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{
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/* Disallow writes to the vital product data */
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if (value & PCI_VPD_ADDR_F)
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return PCIBIOS_SET_FAILED;
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else
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return pci_write_config_word(dev, offset, value);
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}
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static const struct config_field caplist_vpd[] = {
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{
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.offset = PCI_VPD_ADDR,
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.size = 2,
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.u.w.read = xen_pcibk_read_config_word,
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.u.w.write = vpd_address_write,
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},
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{
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.offset = PCI_VPD_DATA,
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.size = 4,
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.u.dw.read = xen_pcibk_read_config_dword,
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.u.dw.write = NULL,
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},
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{}
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};
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static int pm_caps_read(struct pci_dev *dev, int offset, u16 *value,
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void *data)
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{
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int err;
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u16 real_value;
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err = pci_read_config_word(dev, offset, &real_value);
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if (err)
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goto out;
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*value = real_value & ~PCI_PM_CAP_PME_MASK;
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out:
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return err;
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}
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/* PM_OK_BITS specifies the bits that the driver domain is allowed to change.
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* Can't allow driver domain to enable PMEs - they're shared */
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#define PM_OK_BITS (PCI_PM_CTRL_PME_STATUS|PCI_PM_CTRL_DATA_SEL_MASK)
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static int pm_ctrl_write(struct pci_dev *dev, int offset, u16 new_value,
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void *data)
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{
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int err;
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u16 old_value;
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pci_power_t new_state;
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err = pci_read_config_word(dev, offset, &old_value);
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if (err)
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goto out;
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new_state = (pci_power_t)(new_value & PCI_PM_CTRL_STATE_MASK);
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new_value &= PM_OK_BITS;
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if ((old_value & PM_OK_BITS) != new_value) {
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new_value = (old_value & ~PM_OK_BITS) | new_value;
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err = pci_write_config_word(dev, offset, new_value);
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if (err)
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goto out;
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}
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/* Let pci core handle the power management change */
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dev_dbg(&dev->dev, "set power state to %x\n", new_state);
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err = pci_set_power_state(dev, new_state);
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if (err) {
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err = PCIBIOS_SET_FAILED;
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goto out;
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}
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out:
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return err;
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}
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/* Ensure PMEs are disabled */
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static void *pm_ctrl_init(struct pci_dev *dev, int offset)
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{
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int err;
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u16 value;
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err = pci_read_config_word(dev, offset, &value);
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if (err)
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goto out;
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if (value & PCI_PM_CTRL_PME_ENABLE) {
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value &= ~PCI_PM_CTRL_PME_ENABLE;
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err = pci_write_config_word(dev, offset, value);
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}
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out:
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return err ? ERR_PTR(err) : NULL;
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}
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static const struct config_field caplist_pm[] = {
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{
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.offset = PCI_PM_PMC,
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.size = 2,
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.u.w.read = pm_caps_read,
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},
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{
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.offset = PCI_PM_CTRL,
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.size = 2,
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.init = pm_ctrl_init,
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.u.w.read = xen_pcibk_read_config_word,
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.u.w.write = pm_ctrl_write,
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},
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{
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.offset = PCI_PM_PPB_EXTENSIONS,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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},
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{
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.offset = PCI_PM_DATA_REGISTER,
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.size = 1,
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.u.b.read = xen_pcibk_read_config_byte,
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},
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{}
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};
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static struct msi_msix_field_config {
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u16 enable_bit; /* bit for enabling MSI/MSI-X */
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unsigned int int_type; /* interrupt type for exclusiveness check */
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} msi_field_config = {
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.enable_bit = PCI_MSI_FLAGS_ENABLE,
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.int_type = INTERRUPT_TYPE_MSI,
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}, msix_field_config = {
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.enable_bit = PCI_MSIX_FLAGS_ENABLE,
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.int_type = INTERRUPT_TYPE_MSIX,
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};
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static void *msi_field_init(struct pci_dev *dev, int offset)
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{
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return &msi_field_config;
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}
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static void *msix_field_init(struct pci_dev *dev, int offset)
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{
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return &msix_field_config;
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}
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static int msi_msix_flags_write(struct pci_dev *dev, int offset, u16 new_value,
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void *data)
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{
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int err;
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u16 old_value;
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const struct msi_msix_field_config *field_config = data;
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const struct xen_pcibk_dev_data *dev_data = pci_get_drvdata(dev);
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if (xen_pcibk_permissive || dev_data->permissive)
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goto write;
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err = pci_read_config_word(dev, offset, &old_value);
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if (err)
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return err;
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if (new_value == old_value)
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return 0;
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if (!dev_data->allow_interrupt_control ||
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(new_value ^ old_value) & ~field_config->enable_bit)
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return PCIBIOS_SET_FAILED;
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if (new_value & field_config->enable_bit) {
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/* don't allow enabling together with other interrupt types */
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int int_type = xen_pcibk_get_interrupt_type(dev);
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if (int_type == INTERRUPT_TYPE_NONE ||
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int_type == field_config->int_type)
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goto write;
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return PCIBIOS_SET_FAILED;
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}
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write:
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return pci_write_config_word(dev, offset, new_value);
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}
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static const struct config_field caplist_msix[] = {
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{
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.offset = PCI_MSIX_FLAGS,
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.size = 2,
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.init = msix_field_init,
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.u.w.read = xen_pcibk_read_config_word,
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.u.w.write = msi_msix_flags_write,
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},
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{}
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};
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static const struct config_field caplist_msi[] = {
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{
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.offset = PCI_MSI_FLAGS,
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.size = 2,
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.init = msi_field_init,
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.u.w.read = xen_pcibk_read_config_word,
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.u.w.write = msi_msix_flags_write,
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},
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{}
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};
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static struct xen_pcibk_config_capability xen_pcibk_config_capability_pm = {
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.capability = PCI_CAP_ID_PM,
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.fields = caplist_pm,
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};
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static struct xen_pcibk_config_capability xen_pcibk_config_capability_vpd = {
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.capability = PCI_CAP_ID_VPD,
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.fields = caplist_vpd,
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};
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static struct xen_pcibk_config_capability xen_pcibk_config_capability_msi = {
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.capability = PCI_CAP_ID_MSI,
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.fields = caplist_msi,
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};
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static struct xen_pcibk_config_capability xen_pcibk_config_capability_msix = {
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.capability = PCI_CAP_ID_MSIX,
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.fields = caplist_msix,
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};
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int xen_pcibk_config_capability_init(void)
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{
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register_capability(&xen_pcibk_config_capability_vpd);
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register_capability(&xen_pcibk_config_capability_pm);
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register_capability(&xen_pcibk_config_capability_msi);
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register_capability(&xen_pcibk_config_capability_msix);
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return 0;
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}
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