171 lines
4.9 KiB
C
171 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#define WDTRSTCR_RESET 0xA55A0002
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#define WDTRSTCR 0x0054
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#define CR7BAR 0x0070
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#define CR7BAREN BIT(4)
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#define CR7BAR_MASK 0xFFFC0000
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static void __iomem *rcar_rst_base;
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static u32 saved_mode __initdata;
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static int (*rcar_rst_set_rproc_boot_addr_func)(u64 boot_addr);
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static int rcar_rst_enable_wdt_reset(void __iomem *base)
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{
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iowrite32(WDTRSTCR_RESET, base + WDTRSTCR);
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return 0;
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}
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/*
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* Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
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* Firmware boot address has to be set in CR7BAR before
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* starting the realtime core.
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* Boot address must be aligned on a 256k boundary.
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*/
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static int rcar_rst_set_gen3_rproc_boot_addr(u64 boot_addr)
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{
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if (boot_addr & ~(u64)CR7BAR_MASK) {
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pr_err("Invalid boot address got %llx\n", boot_addr);
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return -EINVAL;
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}
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iowrite32(boot_addr, rcar_rst_base + CR7BAR);
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iowrite32(boot_addr | CR7BAREN, rcar_rst_base + CR7BAR);
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return 0;
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}
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struct rst_config {
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unsigned int modemr; /* Mode Monitoring Register Offset */
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int (*configure)(void __iomem *base); /* Platform specific config */
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int (*set_rproc_boot_addr)(u64 boot_addr);
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};
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static const struct rst_config rcar_rst_gen1 __initconst = {
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.modemr = 0x20,
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};
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static const struct rst_config rcar_rst_gen2 __initconst = {
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.modemr = 0x60,
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.configure = rcar_rst_enable_wdt_reset,
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};
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static const struct rst_config rcar_rst_gen3 __initconst = {
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.modemr = 0x60,
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.set_rproc_boot_addr = rcar_rst_set_gen3_rproc_boot_addr,
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};
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static const struct rst_config rcar_rst_gen4 __initconst = {
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.modemr = 0x00, /* MODEMR0 and it has CPG related bits */
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};
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static const struct of_device_id rcar_rst_matches[] __initconst = {
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/* RZ/G1 is handled like R-Car Gen2 */
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{ .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a77470-rst", .data = &rcar_rst_gen2 },
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/* RZ/G2 is handled like R-Car Gen3 */
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{ .compatible = "renesas,r8a774a1-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774b1-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774c0-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a774e1-rst", .data = &rcar_rst_gen3 },
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/* R-Car Gen1 */
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{ .compatible = "renesas,r8a7778-reset-wdt", .data = &rcar_rst_gen1 },
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{ .compatible = "renesas,r8a7779-reset-wdt", .data = &rcar_rst_gen1 },
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/* R-Car Gen2 */
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{ .compatible = "renesas,r8a7790-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7791-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7792-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7793-rst", .data = &rcar_rst_gen2 },
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{ .compatible = "renesas,r8a7794-rst", .data = &rcar_rst_gen2 },
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/* R-Car Gen3 */
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{ .compatible = "renesas,r8a7795-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a7796-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77961-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77965-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77970-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77980-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77990-rst", .data = &rcar_rst_gen3 },
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{ .compatible = "renesas,r8a77995-rst", .data = &rcar_rst_gen3 },
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/* R-Car Gen4 */
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{ .compatible = "renesas,r8a779a0-rst", .data = &rcar_rst_gen4 },
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{ .compatible = "renesas,r8a779f0-rst", .data = &rcar_rst_gen4 },
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{ /* sentinel */ }
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};
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static int __init rcar_rst_init(void)
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{
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const struct of_device_id *match;
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const struct rst_config *cfg;
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struct device_node *np;
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void __iomem *base;
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int error = 0;
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np = of_find_matching_node_and_match(NULL, rcar_rst_matches, &match);
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if (!np)
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return -ENODEV;
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("%pOF: Cannot map regs\n", np);
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error = -ENOMEM;
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goto out_put;
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}
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rcar_rst_base = base;
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cfg = match->data;
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rcar_rst_set_rproc_boot_addr_func = cfg->set_rproc_boot_addr;
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saved_mode = ioread32(base + cfg->modemr);
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if (cfg->configure) {
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error = cfg->configure(base);
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if (error) {
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pr_warn("%pOF: Cannot run SoC specific configuration\n",
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np);
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goto out_put;
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}
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}
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pr_debug("%pOF: MODE = 0x%08x\n", np, saved_mode);
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out_put:
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of_node_put(np);
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return error;
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}
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int __init rcar_rst_read_mode_pins(u32 *mode)
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{
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int error;
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if (!rcar_rst_base) {
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error = rcar_rst_init();
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if (error)
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return error;
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}
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*mode = saved_mode;
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return 0;
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}
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int rcar_rst_set_rproc_boot_addr(u64 boot_addr)
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{
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if (!rcar_rst_set_rproc_boot_addr_func)
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return -EIO;
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return rcar_rst_set_rproc_boot_addr_func(boot_addr);
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}
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EXPORT_SYMBOL_GPL(rcar_rst_set_rproc_boot_addr);
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