266 lines
7.9 KiB
C
266 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8183-power.h>
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/*
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* MT8183 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
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[MT8183_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = 0x0314,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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},
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[MT8183_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = 0x032c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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},
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[MT8183_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = 0x0334,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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},
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[MT8183_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = 0x0338,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.caps = MTK_SCPD_DOMAIN_SUPPLY,
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},
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[MT8183_POWER_DOMAIN_MFG_CORE0] = {
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.name = "mfg_core0",
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.sta_mask = BIT(7),
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.ctl_offs = 0x034c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_CORE1] = {
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.name = "mfg_core1",
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.sta_mask = BIT(20),
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.ctl_offs = 0x0310,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8183_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = 0x0348,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
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MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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},
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[MT8183_POWER_DOMAIN_DISP] = {
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.name = "disp",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = 0x030c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
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MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_CAM] = {
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.name = "cam",
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.sta_mask = BIT(25),
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.ctl_offs = 0x0344,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = 0x0308,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(9, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = BIT(31),
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.ctl_offs = 0x0300,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = 0x0304,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VPU_TOP] = {
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.name = "vpu_top",
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.sta_mask = BIT(26),
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.ctl_offs = 0x0324,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
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MT8183_TOP_AXI_PROT_EN_SET,
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MT8183_TOP_AXI_PROT_EN_CLR,
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MT8183_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
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MT8183_TOP_AXI_PROT_EN_MM_SET,
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MT8183_TOP_AXI_PROT_EN_MM_CLR,
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MT8183_TOP_AXI_PROT_EN_MM_STA1),
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},
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.bp_smi = {
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BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
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MT8183_SMI_COMMON_CLAMP_EN_SET,
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MT8183_SMI_COMMON_CLAMP_EN_CLR,
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MT8183_SMI_COMMON_CLAMP_EN),
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},
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},
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[MT8183_POWER_DOMAIN_VPU_CORE0] = {
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.name = "vpu_core0",
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.sta_mask = BIT(27),
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.ctl_offs = 0x33c,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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},
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.caps = MTK_SCPD_SRAM_ISO,
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},
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[MT8183_POWER_DOMAIN_VPU_CORE1] = {
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.name = "vpu_core1",
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.sta_mask = BIT(28),
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.ctl_offs = 0x0340,
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.pwr_sta_offs = 0x0180,
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.pwr_sta2nd_offs = 0x0184,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
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MT8183_TOP_AXI_PROT_EN_MCU_SET,
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MT8183_TOP_AXI_PROT_EN_MCU_CLR,
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MT8183_TOP_AXI_PROT_EN_MCU_STA1),
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},
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.caps = MTK_SCPD_SRAM_ISO,
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},
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};
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static const struct scpsys_soc_data mt8183_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8183,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
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};
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#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */
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