171 lines
4.5 KiB
C
171 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* SP7021 Pin Controller Driver.
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* Copyright (C) Sunplus Tech / Tibbo Tech.
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*/
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#ifndef __SPPCTL_H__
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#define __SPPCTL_H__
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/kernel.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define SPPCTL_MODULE_NAME "sppctl_sp7021"
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#define SPPCTL_GPIO_OFF_FIRST 0x00
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#define SPPCTL_GPIO_OFF_MASTER 0x00
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#define SPPCTL_GPIO_OFF_OE 0x20
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#define SPPCTL_GPIO_OFF_OUT 0x40
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#define SPPCTL_GPIO_OFF_IN 0x60
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#define SPPCTL_GPIO_OFF_IINV 0x80
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#define SPPCTL_GPIO_OFF_OINV 0xa0
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#define SPPCTL_GPIO_OFF_OD 0xc0
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#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16)
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#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0)
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#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8
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/*
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* Mask-fields and control-fields of MOON registers of SP7021 are
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* arranged as shown below:
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*
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* register | mask-fields | control-fields
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* ----------+--------------+----------------
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* base[0] | (31 : 16) | (15 : 0)
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* base[1] | (31 : 24) | (15 : 0)
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* base[2] | (31 : 24) | (15 : 0)
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* : | : | :
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*
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* where mask-fields are used to protect control-fields from write-in
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* accidentally. Set the corresponding bits in the mask-field before
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* you write a value into a control-field.
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*/
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#define SPPCTL_MOON_REG_MASK_SHIFT 16
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#define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit))
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#define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT)
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#define SPPCTL_IOP_CONFIGS 0xff
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#define FNCE(n, r, o, bo, bl, g) { \
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.name = n, \
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.type = r, \
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.roff = o, \
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.boff = bo, \
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.blen = bl, \
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.grps = (g), \
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.gnum = ARRAY_SIZE(g), \
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}
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#define FNCN(n, r, o, bo, bl) { \
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.name = n, \
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.type = r, \
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.roff = o, \
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.boff = bo, \
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.blen = bl, \
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.grps = NULL, \
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.gnum = 0, \
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}
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#define EGRP(n, v, p) { \
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.name = n, \
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.gval = (v), \
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.pins = (p), \
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.pnum = ARRAY_SIZE(p), \
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}
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/**
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* enum mux_first_reg - Define modes of access of FIRST register
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* @mux_f_mux: Set the corresponding pin to a fully-pinmux pin
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* @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin
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* @mux_f_keep: Don't change (keep intact)
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*/
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enum mux_first_reg {
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mux_f_mux = 0,
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mux_f_gpio = 1,
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mux_f_keep = 2,
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};
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/**
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* enum mux_master_reg - Define modes of access of MASTER register
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* @mux_m_iop: Set the corresponding pin to an IO processor (IOP) pin
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* @mux_m_gpio: Set the corresponding pin to a digital GPIO pin
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* @mux_m_keep: Don't change (keep intact)
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*/
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enum mux_master_reg {
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mux_m_iop = 0,
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mux_m_gpio = 1,
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mux_m_keep = 2,
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};
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/**
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* enum pinmux_type - Define types of pinmux pins
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* @pinmux_type_fpmx: A fully-pinmux pin
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* @pinmux_type_grp: A group-pinmux pin
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*/
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enum pinmux_type {
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pinmux_type_fpmx,
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pinmux_type_grp,
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};
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/**
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* struct grp2fp_map - A map storing indexes
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* @f_idx: an index to function table
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* @g_idx: an index to group table
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*/
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struct grp2fp_map {
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u16 f_idx;
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u16 g_idx;
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};
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struct sppctl_gpio_chip;
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struct sppctl_pdata {
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void __iomem *moon2_base; /* MOON2 */
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void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
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void __iomem *first_base; /* FIRST */
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void __iomem *moon1_base; /* MOON1 */
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struct pinctrl_desc pctl_desc;
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struct pinctrl_dev *pctl_dev;
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struct pinctrl_gpio_range pctl_grange;
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struct sppctl_gpio_chip *spp_gchip;
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char const **unq_grps;
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size_t unq_grps_sz;
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struct grp2fp_map *g2fp_maps;
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};
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struct sppctl_grp {
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const char * const name;
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const u8 gval; /* group number */
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const unsigned * const pins; /* list of pins */
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const unsigned int pnum; /* number of pins */
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};
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struct sppctl_func {
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const char * const name;
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const enum pinmux_type type; /* function type */
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const u8 roff; /* register offset */
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const u8 boff; /* bit offset */
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const u8 blen; /* bit length */
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const struct sppctl_grp * const grps; /* list of groups */
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const unsigned int gnum; /* number of groups */
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};
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extern const struct sppctl_func sppctl_list_funcs[];
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extern const char * const sppctl_pmux_list_s[];
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extern const char * const sppctl_gpio_list_s[];
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extern const struct pinctrl_pin_desc sppctl_pins_all[];
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extern const unsigned int sppctl_pins_gpio[];
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extern const size_t sppctl_list_funcs_sz;
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extern const size_t sppctl_pmux_list_sz;
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extern const size_t sppctl_gpio_list_sz;
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extern const size_t sppctl_pins_all_sz;
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#endif
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