525 lines
15 KiB
C
525 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Apple SoC pinctrl+GPIO+external IRQ driver
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*
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* Copyright (C) The Asahi Linux Contributors
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* Copyright (C) 2020 Corellium LLC
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*
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* Based on: pinctrl-pistachio.c
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* Copyright (C) 2014 Imagination Technologies Ltd.
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* Copyright (C) 2014 Google, Inc.
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*/
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#include <dt-bindings/pinctrl/apple.h>
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "pinctrl-utils.h"
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#include "core.h"
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#include "pinmux.h"
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struct apple_gpio_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctldev;
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void __iomem *base;
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struct regmap *map;
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struct pinctrl_desc pinctrl_desc;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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u8 irqgrps[];
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};
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#define REG_GPIO(x) (4 * (x))
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#define REG_GPIOx_DATA BIT(0)
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#define REG_GPIOx_MODE GENMASK(3, 1)
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#define REG_GPIOx_OUT 1
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#define REG_GPIOx_IN_IRQ_HI 2
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#define REG_GPIOx_IN_IRQ_LO 3
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#define REG_GPIOx_IN_IRQ_UP 4
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#define REG_GPIOx_IN_IRQ_DN 5
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#define REG_GPIOx_IN_IRQ_ANY 6
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#define REG_GPIOx_IN_IRQ_OFF 7
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#define REG_GPIOx_PERIPH GENMASK(6, 5)
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#define REG_GPIOx_PULL GENMASK(8, 7)
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#define REG_GPIOx_PULL_OFF 0
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#define REG_GPIOx_PULL_DOWN 1
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#define REG_GPIOx_PULL_UP_STRONG 2
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#define REG_GPIOx_PULL_UP 3
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#define REG_GPIOx_INPUT_ENABLE BIT(9)
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#define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
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#define REG_GPIOx_SCHMITT BIT(15)
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#define REG_GPIOx_GRP GENMASK(18, 16)
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#define REG_GPIOx_LOCK BIT(21)
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#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
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#define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
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struct regmap_config regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.cache_type = REGCACHE_FLAT,
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.max_register = 512 * sizeof(u32),
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.num_reg_defaults_raw = 512,
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.use_relaxed_mmio = true,
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.use_raw_spinlock = true,
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};
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/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
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static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
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unsigned int pin, u32 mask, u32 value)
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{
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regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
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}
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static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
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unsigned int pin)
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{
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int ret;
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u32 val;
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ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
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if (ret)
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return 0;
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return val;
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}
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/* Pin controller functions */
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static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *node,
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struct pinctrl_map **map,
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unsigned *num_maps)
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{
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unsigned reserved_maps;
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struct apple_gpio_pinctrl *pctl;
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u32 pinfunc, pin, func;
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int num_pins, i, ret;
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const char *group_name;
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const char *function_name;
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*map = NULL;
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*num_maps = 0;
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reserved_maps = 0;
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pctl = pinctrl_dev_get_drvdata(pctldev);
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ret = of_property_count_u32_elems(node, "pinmux");
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if (ret <= 0) {
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dev_err(pctl->dev,
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"missing or empty pinmux property in node %pOFn.\n",
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node);
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return ret ? ret : -EINVAL;
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}
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num_pins = ret;
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ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
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if (ret)
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return ret;
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for (i = 0; i < num_pins; i++) {
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ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
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if (ret)
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goto free_map;
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pin = APPLE_PIN(pinfunc);
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func = APPLE_FUNC(pinfunc);
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if (func >= pinmux_generic_get_function_count(pctldev)) {
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ret = -EINVAL;
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goto free_map;
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}
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group_name = pinctrl_generic_get_group_name(pctldev, pin);
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function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
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ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
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&reserved_maps, num_maps,
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group_name, function_name);
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if (ret)
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goto free_map;
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}
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free_map:
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if (ret < 0)
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pinctrl_utils_free_map(pctldev, *map, *num_maps);
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return ret;
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}
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static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
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.get_groups_count = pinctrl_generic_get_group_count,
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.get_group_name = pinctrl_generic_get_group_name,
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.get_group_pins = pinctrl_generic_get_group_pins,
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.dt_node_to_map = apple_gpio_dt_node_to_map,
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.dt_free_map = pinctrl_utils_free_map,
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};
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/* Pin multiplexer functions */
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static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
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unsigned group)
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{
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struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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apple_gpio_set_reg(
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pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
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FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
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return 0;
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}
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static const struct pinmux_ops apple_gpio_pinmux_ops = {
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.get_functions_count = pinmux_generic_get_function_count,
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.get_function_name = pinmux_generic_get_function_name,
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.get_function_groups = pinmux_generic_get_function_groups,
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.set_mux = apple_gpio_pinmux_set,
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.strict = true,
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};
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/* GPIO chip functions */
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static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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unsigned int reg = apple_gpio_get_reg(pctl, offset);
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if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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unsigned int reg = apple_gpio_get_reg(pctl, offset);
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/*
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* If this is an input GPIO, read the actual value (not the
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* cached regmap value)
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*/
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if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
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reg = readl_relaxed(pctl->base + REG_GPIO(offset));
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return !!(reg & REG_GPIOx_DATA);
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}
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static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
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}
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static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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apple_gpio_set_reg(pctl, offset,
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REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
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REG_GPIOx_INPUT_ENABLE,
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FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
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REG_GPIOx_INPUT_ENABLE);
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return 0;
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}
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static int apple_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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apple_gpio_set_reg(pctl, offset,
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REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
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FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
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(value ? REG_GPIOx_DATA : 0));
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return 0;
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}
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/* IRQ chip functions */
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static void apple_gpio_irq_ack(struct irq_data *data)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
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writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
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}
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static unsigned int apple_gpio_irq_type(unsigned int type)
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{
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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return REG_GPIOx_IN_IRQ_UP;
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case IRQ_TYPE_EDGE_FALLING:
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return REG_GPIOx_IN_IRQ_DN;
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case IRQ_TYPE_EDGE_BOTH:
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return REG_GPIOx_IN_IRQ_ANY;
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case IRQ_TYPE_LEVEL_HIGH:
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return REG_GPIOx_IN_IRQ_HI;
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case IRQ_TYPE_LEVEL_LOW:
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return REG_GPIOx_IN_IRQ_LO;
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default:
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return REG_GPIOx_IN_IRQ_OFF;
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}
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}
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static void apple_gpio_irq_mask(struct irq_data *data)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
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apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
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FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
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}
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static void apple_gpio_irq_unmask(struct irq_data *data)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
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apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
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FIELD_PREP(REG_GPIOx_MODE, irqtype));
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}
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static unsigned int apple_gpio_irq_startup(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
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apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
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FIELD_PREP(REG_GPIOx_GRP, 0));
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apple_gpio_direction_input(chip, data->hwirq);
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apple_gpio_irq_unmask(data);
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return 0;
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}
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static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
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unsigned int irqtype = apple_gpio_irq_type(type);
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if (irqtype == REG_GPIOx_IN_IRQ_OFF)
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return -EINVAL;
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apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
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FIELD_PREP(REG_GPIOx_MODE, irqtype));
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if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(data, handle_level_irq);
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else
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irq_set_handler_locked(data, handle_edge_irq);
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return 0;
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}
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static void apple_gpio_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u8 *grpp = irq_desc_get_handler_data(desc);
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struct apple_gpio_pinctrl *pctl;
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unsigned int pinh, pinl;
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unsigned long pending;
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struct gpio_chip *gc;
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pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
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gc = &pctl->gpio_chip;
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chained_irq_enter(chip, desc);
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for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
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pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
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for_each_set_bit(pinl, &pending, 32)
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generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
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}
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip apple_gpio_irqchip = {
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.name = "Apple-GPIO",
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.irq_startup = apple_gpio_irq_startup,
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.irq_ack = apple_gpio_irq_ack,
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.irq_mask = apple_gpio_irq_mask,
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.irq_unmask = apple_gpio_irq_unmask,
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.irq_set_type = apple_gpio_irq_set_type,
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};
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/* Probe & register */
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static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
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{
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struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
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void **irq_data = NULL;
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int ret;
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pctl->irq_chip = apple_gpio_irqchip;
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pctl->gpio_chip.label = dev_name(pctl->dev);
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pctl->gpio_chip.request = gpiochip_generic_request;
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pctl->gpio_chip.free = gpiochip_generic_free;
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pctl->gpio_chip.get_direction = apple_gpio_get_direction;
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pctl->gpio_chip.direction_input = apple_gpio_direction_input;
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pctl->gpio_chip.direction_output = apple_gpio_direction_output;
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pctl->gpio_chip.get = apple_gpio_get;
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pctl->gpio_chip.set = apple_gpio_set;
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pctl->gpio_chip.base = -1;
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pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
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pctl->gpio_chip.parent = pctl->dev;
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if (girq->num_parents) {
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int i;
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girq->chip = &pctl->irq_chip;
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girq->parent_handler = apple_gpio_irq_handler;
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girq->parents = kmalloc_array(girq->num_parents,
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sizeof(*girq->parents),
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GFP_KERNEL);
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irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
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GFP_KERNEL);
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if (!girq->parents || !irq_data) {
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ret = -ENOMEM;
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goto out_free_irq_data;
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}
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for (i = 0; i < girq->num_parents; i++) {
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ret = platform_get_irq(to_platform_device(pctl->dev), i);
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if (ret < 0)
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goto out_free_irq_data;
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girq->parents[i] = ret;
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pctl->irqgrps[i] = i;
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irq_data[i] = &pctl->irqgrps[i];
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}
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girq->parent_handler_data_array = irq_data;
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girq->per_parent_data = true;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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}
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ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
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out_free_irq_data:
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kfree(girq->parents);
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kfree(irq_data);
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return ret;
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}
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static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
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{
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struct apple_gpio_pinctrl *pctl;
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struct pinctrl_pin_desc *pins;
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unsigned int npins;
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const char **pin_names;
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unsigned int *pin_nums;
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static const char* pinmux_functions[] = {
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"gpio", "periph1", "periph2", "periph3"
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};
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unsigned int i, nirqs = 0;
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int res;
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if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
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res = platform_irq_count(pdev);
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if (res > 0)
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nirqs = res;
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}
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pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
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GFP_KERNEL);
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if (!pctl)
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return -ENOMEM;
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pctl->dev = &pdev->dev;
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pctl->gpio_chip.irq.num_parents = nirqs;
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dev_set_drvdata(&pdev->dev, pctl);
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if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
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return dev_err_probe(&pdev->dev, -EINVAL,
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"apple,npins property not found\n");
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pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
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GFP_KERNEL);
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pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
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GFP_KERNEL);
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pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
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GFP_KERNEL);
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if (!pins || !pin_names || !pin_nums)
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return -ENOMEM;
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pctl->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pctl->base))
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return PTR_ERR(pctl->base);
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pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config);
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if (IS_ERR(pctl->map))
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return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
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"Failed to create regmap\n");
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for (i = 0; i < npins; i++) {
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pins[i].number = i;
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|
pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
|
|
pins[i].drv_data = pctl;
|
|
pin_names[i] = pins[i].name;
|
|
pin_nums[i] = i;
|
|
}
|
|
|
|
pctl->pinctrl_desc.name = dev_name(pctl->dev);
|
|
pctl->pinctrl_desc.pins = pins;
|
|
pctl->pinctrl_desc.npins = npins;
|
|
pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
|
|
pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
|
|
|
|
pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
|
|
if (IS_ERR(pctl->pctldev))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
|
|
"Failed to register pinctrl device.\n");
|
|
|
|
for (i = 0; i < npins; i++) {
|
|
res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
|
|
pin_nums + i, 1, pctl);
|
|
if (res < 0)
|
|
return dev_err_probe(pctl->dev, res,
|
|
"Failed to register group");
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
|
|
res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
|
|
pin_names, npins, pctl);
|
|
if (res < 0)
|
|
return dev_err_probe(pctl->dev, res,
|
|
"Failed to register function.");
|
|
}
|
|
|
|
return apple_gpio_register(pctl);
|
|
}
|
|
|
|
static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
|
|
{ .compatible = "apple,pinctrl", },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver apple_gpio_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "apple-gpio-pinctrl",
|
|
.of_match_table = apple_gpio_pinctrl_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = apple_gpio_pinctrl_probe,
|
|
};
|
|
module_platform_driver(apple_gpio_pinctrl_driver);
|
|
|
|
MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
|
|
MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
|
|
MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
|
|
MODULE_LICENSE("GPL v2");
|