515 lines
12 KiB
C
515 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2014-2018 MediaTek Inc.
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/*
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* Library for MediaTek External Interrupt Support
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*
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* Author: Maoguang Meng <maoguang.meng@mediatek.com>
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* Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include "mtk-eint.h"
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#define MTK_EINT_EDGE_SENSITIVE 0
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#define MTK_EINT_LEVEL_SENSITIVE 1
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#define MTK_EINT_DBNC_SET_DBNC_BITS 4
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#define MTK_EINT_DBNC_RST_BIT (0x1 << 1)
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#define MTK_EINT_DBNC_SET_EN (0x1 << 0)
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static const struct mtk_eint_regs mtk_generic_eint_regs = {
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.stat = 0x000,
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.ack = 0x040,
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.mask = 0x080,
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.mask_set = 0x0c0,
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.mask_clr = 0x100,
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.sens = 0x140,
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.sens_set = 0x180,
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.sens_clr = 0x1c0,
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.soft = 0x200,
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.soft_set = 0x240,
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.soft_clr = 0x280,
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.pol = 0x300,
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.pol_set = 0x340,
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.pol_clr = 0x380,
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.dom_en = 0x400,
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.dbnc_ctrl = 0x500,
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.dbnc_set = 0x600,
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.dbnc_clr = 0x700,
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};
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static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
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unsigned int eint_num,
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unsigned int offset)
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{
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unsigned int eint_base = 0;
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void __iomem *reg;
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if (eint_num >= eint->hw->ap_num)
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eint_base = eint->hw->ap_num;
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reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
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return reg;
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}
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static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
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unsigned int eint_num)
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{
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unsigned int sens;
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unsigned int bit = BIT(eint_num % 32);
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void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
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eint->regs->sens);
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if (readl(reg) & bit)
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sens = MTK_EINT_LEVEL_SENSITIVE;
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else
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sens = MTK_EINT_EDGE_SENSITIVE;
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if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
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return 1;
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else
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return 0;
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}
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static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
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{
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int start_level, curr_level;
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unsigned int reg_offset;
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u32 mask = BIT(hwirq & 0x1f);
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u32 port = (hwirq >> 5) & eint->hw->port_mask;
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void __iomem *reg = eint->base + (port << 2);
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curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
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do {
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start_level = curr_level;
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if (start_level)
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reg_offset = eint->regs->pol_clr;
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else
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reg_offset = eint->regs->pol_set;
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writel(mask, reg + reg_offset);
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curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
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hwirq);
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} while (start_level != curr_level);
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return start_level;
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}
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static void mtk_eint_mask(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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eint->regs->mask_set);
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eint->cur_mask[d->hwirq >> 5] &= ~mask;
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writel(mask, reg);
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}
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static void mtk_eint_unmask(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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eint->regs->mask_clr);
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eint->cur_mask[d->hwirq >> 5] |= mask;
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writel(mask, reg);
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if (eint->dual_edge[d->hwirq])
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mtk_eint_flip_edge(eint, d->hwirq);
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}
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static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
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unsigned int eint_num)
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{
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unsigned int bit = BIT(eint_num % 32);
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void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
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eint->regs->mask);
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return !!(readl(reg) & bit);
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}
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static void mtk_eint_ack(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
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eint->regs->ack);
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writel(mask, reg);
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}
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static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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bool masked;
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u32 mask = BIT(d->hwirq & 0x1f);
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void __iomem *reg;
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if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
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((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
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dev_err(eint->dev,
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"Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
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d->irq, d->hwirq, type);
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return -EINVAL;
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}
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if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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eint->dual_edge[d->hwirq] = 1;
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else
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eint->dual_edge[d->hwirq] = 0;
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if (!mtk_eint_get_mask(eint, d->hwirq)) {
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mtk_eint_mask(d);
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masked = false;
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} else {
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masked = true;
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}
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
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reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
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writel(mask, reg);
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} else {
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reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
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writel(mask, reg);
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}
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
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reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
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writel(mask, reg);
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} else {
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reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
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writel(mask, reg);
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}
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mtk_eint_ack(d);
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if (!masked)
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mtk_eint_unmask(d);
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return 0;
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}
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static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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int shift = d->hwirq & 0x1f;
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int reg = d->hwirq >> 5;
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if (on)
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eint->wake_mask[reg] |= BIT(shift);
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else
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eint->wake_mask[reg] &= ~BIT(shift);
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return 0;
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}
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static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
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void __iomem *base, u32 *buf)
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{
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int port;
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void __iomem *reg;
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for (port = 0; port < eint->hw->ports; port++) {
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reg = base + (port << 2);
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writel_relaxed(~buf[port], reg + eint->regs->mask_set);
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writel_relaxed(buf[port], reg + eint->regs->mask_clr);
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}
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}
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static int mtk_eint_irq_request_resources(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gpio_c;
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unsigned int gpio_n;
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int err;
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err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
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&gpio_n, &gpio_c);
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if (err < 0) {
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dev_err(eint->dev, "Can not find pin\n");
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return err;
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}
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err = gpiochip_lock_as_irq(gpio_c, gpio_n);
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if (err < 0) {
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dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return err;
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}
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err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
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if (err < 0) {
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dev_err(eint->dev, "Can not eint mode\n");
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return err;
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}
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return 0;
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}
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static void mtk_eint_irq_release_resources(struct irq_data *d)
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{
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struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
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struct gpio_chip *gpio_c;
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unsigned int gpio_n;
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eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
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&gpio_c);
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gpiochip_unlock_as_irq(gpio_c, gpio_n);
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}
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static struct irq_chip mtk_eint_irq_chip = {
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.name = "mt-eint",
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.irq_disable = mtk_eint_mask,
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.irq_mask = mtk_eint_mask,
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.irq_unmask = mtk_eint_unmask,
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.irq_ack = mtk_eint_ack,
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.irq_set_type = mtk_eint_set_type,
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.irq_set_wake = mtk_eint_irq_set_wake,
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.irq_request_resources = mtk_eint_irq_request_resources,
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.irq_release_resources = mtk_eint_irq_release_resources,
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};
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static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
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{
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void __iomem *reg = eint->base + eint->regs->dom_en;
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unsigned int i;
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for (i = 0; i < eint->hw->ap_num; i += 32) {
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writel(0xffffffff, reg);
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reg += 4;
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}
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return 0;
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}
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static inline void
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mtk_eint_debounce_process(struct mtk_eint *eint, int index)
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{
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unsigned int rst, ctrl_offset;
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unsigned int bit, dbnc;
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ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
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dbnc = readl(eint->base + ctrl_offset);
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bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
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if ((bit & dbnc) > 0) {
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ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
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rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
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writel(rst, eint->base + ctrl_offset);
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}
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}
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static void mtk_eint_irq_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct mtk_eint *eint = irq_desc_get_handler_data(desc);
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unsigned int status, eint_num;
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int offset, mask_offset, index;
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void __iomem *reg = mtk_eint_get_offset(eint, 0, eint->regs->stat);
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int dual_edge, start_level, curr_level;
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chained_irq_enter(chip, desc);
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for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
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reg += 4) {
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status = readl(reg);
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while (status) {
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offset = __ffs(status);
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mask_offset = eint_num >> 5;
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index = eint_num + offset;
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status &= ~BIT(offset);
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/*
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* If we get an interrupt on pin that was only required
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* for wake (but no real interrupt requested), mask the
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* interrupt (as would mtk_eint_resume do anyway later
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* in the resume sequence).
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*/
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if (eint->wake_mask[mask_offset] & BIT(offset) &&
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!(eint->cur_mask[mask_offset] & BIT(offset))) {
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writel_relaxed(BIT(offset), reg -
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eint->regs->stat +
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eint->regs->mask_set);
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}
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dual_edge = eint->dual_edge[index];
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if (dual_edge) {
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/*
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* Clear soft-irq in case we raised it last
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* time.
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*/
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writel(BIT(offset), reg - eint->regs->stat +
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eint->regs->soft_clr);
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start_level =
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eint->gpio_xlate->get_gpio_state(eint->pctl,
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index);
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}
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generic_handle_domain_irq(eint->domain, index);
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if (dual_edge) {
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curr_level = mtk_eint_flip_edge(eint, index);
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/*
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* If level changed, we might lost one edge
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* interrupt, raised it through soft-irq.
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*/
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if (start_level != curr_level)
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writel(BIT(offset), reg -
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eint->regs->stat +
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eint->regs->soft_set);
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}
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if (index < eint->hw->db_cnt)
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mtk_eint_debounce_process(eint, index);
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}
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}
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chained_irq_exit(chip, desc);
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}
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int mtk_eint_do_suspend(struct mtk_eint *eint)
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{
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mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mtk_eint_do_suspend);
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int mtk_eint_do_resume(struct mtk_eint *eint)
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{
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mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mtk_eint_do_resume);
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int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
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unsigned int debounce)
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{
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int virq, eint_offset;
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unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
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dbnc;
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static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
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64000, 128000, 256000};
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struct irq_data *d;
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virq = irq_find_mapping(eint->domain, eint_num);
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eint_offset = (eint_num % 4) * 8;
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d = irq_get_irq_data(virq);
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set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
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clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
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if (!mtk_eint_can_en_debounce(eint, eint_num))
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return -EINVAL;
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dbnc = ARRAY_SIZE(debounce_time);
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for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
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if (debounce <= debounce_time[i]) {
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dbnc = i;
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break;
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}
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}
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if (!mtk_eint_get_mask(eint, eint_num)) {
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mtk_eint_mask(d);
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unmask = 1;
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} else {
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unmask = 0;
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}
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clr_bit = 0xff << eint_offset;
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writel(clr_bit, eint->base + clr_offset);
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bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
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eint_offset;
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rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
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writel(rst | bit, eint->base + set_offset);
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/*
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* Delay a while (more than 2T) to wait for hw debounce counter reset
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* work correctly.
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*/
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udelay(1);
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if (unmask == 1)
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mtk_eint_unmask(d);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mtk_eint_set_debounce);
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int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
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{
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int irq;
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irq = irq_find_mapping(eint->domain, eint_n);
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if (!irq)
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return -EINVAL;
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return irq;
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}
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EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
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int mtk_eint_do_init(struct mtk_eint *eint)
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{
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int i;
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/* If clients don't assign a specific regs, let's use generic one */
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if (!eint->regs)
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eint->regs = &mtk_generic_eint_regs;
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eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
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sizeof(*eint->wake_mask), GFP_KERNEL);
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if (!eint->wake_mask)
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return -ENOMEM;
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eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
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sizeof(*eint->cur_mask), GFP_KERNEL);
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if (!eint->cur_mask)
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return -ENOMEM;
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|
eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
|
|
sizeof(int), GFP_KERNEL);
|
|
if (!eint->dual_edge)
|
|
return -ENOMEM;
|
|
|
|
eint->domain = irq_domain_add_linear(eint->dev->of_node,
|
|
eint->hw->ap_num,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!eint->domain)
|
|
return -ENOMEM;
|
|
|
|
mtk_eint_hw_init(eint);
|
|
for (i = 0; i < eint->hw->ap_num; i++) {
|
|
int virq = irq_create_mapping(eint->domain, i);
|
|
|
|
irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
|
|
handle_level_irq);
|
|
irq_set_chip_data(virq, eint);
|
|
}
|
|
|
|
irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
|
|
eint);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mtk_eint_do_init);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("MediaTek EINT Driver");
|