546 lines
14 KiB
C
546 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/phy/phy-lan966x-serdes.h>
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#include "lan966x_serdes_regs.h"
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#define PLL_CONF_MASK GENMASK(4, 3)
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#define PLL_CONF_25MHZ 0
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#define PLL_CONF_125MHZ 1
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#define PLL_CONF_SERDES_125MHZ 2
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#define PLL_CONF_BYPASS 3
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#define lan_offset_(id, tinst, tcnt, \
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gbase, ginst, gcnt, gwidth, \
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raddr, rinst, rcnt, rwidth) \
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(gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth))
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#define lan_offset(...) lan_offset_(__VA_ARGS__)
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#define lan_rmw(val, mask, reg, off) \
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lan_rmw_(val, mask, reg, lan_offset(off))
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#define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \
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.idx = _idx, \
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.port = _port, \
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.mode = _mode, \
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.submode = _submode, \
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.mask = _mask, \
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.mux = _mux, \
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}
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#define SERDES_MUX_GMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_GMII, m, c)
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#define SERDES_MUX_SGMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
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#define SERDES_MUX_QSGMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
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#define SERDES_MUX_RGMII(i, p, m, c) \
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SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_RGMII, m, c)
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static void lan_rmw_(u32 val, u32 mask, void __iomem *mem, u32 offset)
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{
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u32 v;
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v = readl(mem + offset);
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v = (v & ~mask) | (val & mask);
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writel(v, mem + offset);
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}
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struct serdes_mux {
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u8 idx;
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u8 port;
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enum phy_mode mode;
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int submode;
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u32 mask;
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u32 mux;
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};
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static const struct serdes_mux lan966x_serdes_muxes[] = {
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SERDES_MUX_QSGMII(SERDES6G(1), 0, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
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SERDES_MUX_QSGMII(SERDES6G(1), 1, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
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SERDES_MUX_QSGMII(SERDES6G(1), 2, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
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SERDES_MUX_QSGMII(SERDES6G(1), 3, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(0))),
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SERDES_MUX_QSGMII(SERDES6G(2), 4, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
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SERDES_MUX_QSGMII(SERDES6G(2), 5, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
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SERDES_MUX_QSGMII(SERDES6G(2), 6, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
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SERDES_MUX_QSGMII(SERDES6G(2), 7, HSIO_HW_CFG_QSGMII_ENA,
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HSIO_HW_CFG_QSGMII_ENA_SET(BIT(1))),
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SERDES_MUX_GMII(CU(0), 0, HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_GMII_ENA_SET(BIT(0))),
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SERDES_MUX_GMII(CU(1), 1, HSIO_HW_CFG_GMII_ENA,
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HSIO_HW_CFG_GMII_ENA_SET(BIT(1))),
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SERDES_MUX_SGMII(SERDES6G(0), 0, HSIO_HW_CFG_SD6G_0_CFG, 0),
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SERDES_MUX_SGMII(SERDES6G(1), 1, HSIO_HW_CFG_SD6G_1_CFG, 0),
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SERDES_MUX_SGMII(SERDES6G(0), 2, HSIO_HW_CFG_SD6G_0_CFG,
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HSIO_HW_CFG_SD6G_0_CFG_SET(1)),
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SERDES_MUX_SGMII(SERDES6G(1), 3, HSIO_HW_CFG_SD6G_1_CFG,
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HSIO_HW_CFG_SD6G_1_CFG_SET(1)),
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SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
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SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
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SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_0_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(0))),
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SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
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HSIO_HW_CFG_RGMII_ENA,
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HSIO_HW_CFG_RGMII_1_CFG_SET(BIT(0)) |
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HSIO_HW_CFG_RGMII_ENA_SET(BIT(1))),
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};
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struct serdes_ctrl {
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void __iomem *regs;
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struct device *dev;
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struct phy *phys[SERDES_MAX];
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int ref125;
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};
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struct serdes_macro {
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u8 idx;
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int port;
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struct serdes_ctrl *ctrl;
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int speed;
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phy_interface_t mode;
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};
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enum lan966x_sd6g40_mode {
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LAN966X_SD6G40_MODE_QSGMII,
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LAN966X_SD6G40_MODE_SGMII,
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};
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enum lan966x_sd6g40_ltx2rx {
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LAN966X_SD6G40_TX2RX_LOOP_NONE,
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LAN966X_SD6G40_LTX2RX
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};
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struct lan966x_sd6g40_setup_args {
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enum lan966x_sd6g40_mode mode;
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enum lan966x_sd6g40_ltx2rx tx2rx_loop;
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bool txinvert;
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bool rxinvert;
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bool refclk125M;
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bool mute;
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};
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struct lan966x_sd6g40_mode_args {
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enum lan966x_sd6g40_mode mode;
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u8 lane_10bit_sel;
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u8 mpll_multiplier;
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u8 ref_clkdiv2;
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u8 tx_rate;
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u8 rx_rate;
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};
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struct lan966x_sd6g40_setup {
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u8 rx_term_en;
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u8 lane_10bit_sel;
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u8 tx_invert;
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u8 rx_invert;
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u8 mpll_multiplier;
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u8 lane_loopbk_en;
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u8 ref_clkdiv2;
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u8 tx_rate;
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u8 rx_rate;
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};
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static int lan966x_sd6g40_reg_cfg(struct serdes_macro *macro,
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struct lan966x_sd6g40_setup *res_struct,
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u32 idx)
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{
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u32 value;
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/* Note: SerDes HSIO is configured in 1G_LAN mode */
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lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) |
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HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) |
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HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) |
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HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) |
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HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) |
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HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) |
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HSIO_SD_CFG_RX_RESET_SET(0) |
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HSIO_SD_CFG_TX_RESET_SET(0),
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HSIO_SD_CFG_LANE_10BIT_SEL |
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HSIO_SD_CFG_RX_RATE |
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HSIO_SD_CFG_TX_RATE |
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HSIO_SD_CFG_TX_INVERT |
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HSIO_SD_CFG_RX_INVERT |
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HSIO_SD_CFG_LANE_LOOPBK_EN |
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HSIO_SD_CFG_RX_RESET |
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HSIO_SD_CFG_TX_RESET,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) |
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HSIO_MPLL_CFG_REF_CLKDIV2_SET(res_struct->ref_clkdiv2),
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HSIO_MPLL_CFG_MPLL_MULTIPLIER |
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HSIO_MPLL_CFG_REF_CLKDIV2,
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macro->ctrl->regs, HSIO_MPLL_CFG(idx));
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lan_rmw(HSIO_SD_CFG_RX_TERM_EN_SET(res_struct->rx_term_en),
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HSIO_SD_CFG_RX_TERM_EN,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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lan_rmw(HSIO_MPLL_CFG_REF_SSP_EN_SET(1),
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HSIO_MPLL_CFG_REF_SSP_EN,
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macro->ctrl->regs, HSIO_MPLL_CFG(idx));
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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lan_rmw(HSIO_SD_CFG_PHY_RESET_SET(0),
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HSIO_SD_CFG_PHY_RESET,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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lan_rmw(HSIO_MPLL_CFG_MPLL_EN_SET(1),
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HSIO_MPLL_CFG_MPLL_EN,
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macro->ctrl->regs, HSIO_MPLL_CFG(idx));
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usleep_range(7 * USEC_PER_MSEC, 8 * USEC_PER_MSEC);
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value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
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value = HSIO_SD_STAT_MPLL_STATE_GET(value);
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if (value != 0x1) {
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dev_err(macro->ctrl->dev,
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"Unexpected sd_sd_stat[%u] mpll_state was 0x1 but is 0x%x\n",
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idx, value);
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return -EIO;
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}
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lan_rmw(HSIO_SD_CFG_TX_CM_EN_SET(1),
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HSIO_SD_CFG_TX_CM_EN,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
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value = HSIO_SD_STAT_TX_CM_STATE_GET(value);
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if (value != 0x1) {
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dev_err(macro->ctrl->dev,
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"Unexpected sd_sd_stat[%u] tx_cm_state was 0x1 but is 0x%x\n",
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idx, value);
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return -EIO;
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}
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lan_rmw(HSIO_SD_CFG_RX_PLL_EN_SET(1) |
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HSIO_SD_CFG_TX_EN_SET(1),
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HSIO_SD_CFG_RX_PLL_EN |
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HSIO_SD_CFG_TX_EN,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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/* Waiting for serdes 0 rx DPLL to lock... */
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value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
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value = HSIO_SD_STAT_RX_PLL_STATE_GET(value);
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if (value != 0x1) {
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dev_err(macro->ctrl->dev,
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"Unexpected sd_sd_stat[%u] rx_pll_state was 0x1 but is 0x%x\n",
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idx, value);
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return -EIO;
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}
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/* Waiting for serdes 0 tx operational... */
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value = readl(macro->ctrl->regs + lan_offset(HSIO_SD_STAT(idx)));
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value = HSIO_SD_STAT_TX_STATE_GET(value);
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if (value != 0x1) {
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dev_err(macro->ctrl->dev,
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"Unexpected sd_sd_stat[%u] tx_state was 0x1 but is 0x%x\n",
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idx, value);
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return -EIO;
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}
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lan_rmw(HSIO_SD_CFG_TX_DATA_EN_SET(1) |
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HSIO_SD_CFG_RX_DATA_EN_SET(1),
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HSIO_SD_CFG_TX_DATA_EN |
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HSIO_SD_CFG_RX_DATA_EN,
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macro->ctrl->regs, HSIO_SD_CFG(idx));
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return 0;
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}
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static int lan966x_sd6g40_get_conf_from_mode(struct serdes_macro *macro,
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enum lan966x_sd6g40_mode f_mode,
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bool ref125M,
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struct lan966x_sd6g40_mode_args *ret_val)
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{
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switch (f_mode) {
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case LAN966X_SD6G40_MODE_QSGMII:
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ret_val->lane_10bit_sel = 0;
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if (ref125M) {
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ret_val->mpll_multiplier = 40;
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ret_val->ref_clkdiv2 = 0x1;
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ret_val->tx_rate = 0x0;
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ret_val->rx_rate = 0x0;
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} else {
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ret_val->mpll_multiplier = 100;
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ret_val->ref_clkdiv2 = 0x0;
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ret_val->tx_rate = 0x0;
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ret_val->rx_rate = 0x0;
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}
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break;
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case LAN966X_SD6G40_MODE_SGMII:
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ret_val->lane_10bit_sel = 1;
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if (ref125M) {
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ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 50 : 40;
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ret_val->ref_clkdiv2 = 0x1;
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ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
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ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
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} else {
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ret_val->mpll_multiplier = macro->speed == SPEED_2500 ? 125 : 100;
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ret_val->ref_clkdiv2 = 0x0;
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ret_val->tx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
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ret_val->rx_rate = macro->speed == SPEED_2500 ? 0x1 : 0x2;
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}
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break;
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int lan966x_calc_sd6g40_setup_lane(struct serdes_macro *macro,
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struct lan966x_sd6g40_setup_args config,
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struct lan966x_sd6g40_setup *ret_val)
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{
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struct lan966x_sd6g40_mode_args sd6g40_mode;
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struct lan966x_sd6g40_mode_args *mode_args = &sd6g40_mode;
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int ret;
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ret = lan966x_sd6g40_get_conf_from_mode(macro, config.mode,
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config.refclk125M, mode_args);
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if (ret)
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return ret;
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ret_val->lane_10bit_sel = mode_args->lane_10bit_sel;
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ret_val->rx_rate = mode_args->rx_rate;
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ret_val->tx_rate = mode_args->tx_rate;
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ret_val->mpll_multiplier = mode_args->mpll_multiplier;
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ret_val->ref_clkdiv2 = mode_args->ref_clkdiv2;
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ret_val->rx_term_en = 0;
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if (config.tx2rx_loop == LAN966X_SD6G40_LTX2RX)
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ret_val->lane_loopbk_en = 1;
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else
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ret_val->lane_loopbk_en = 0;
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ret_val->tx_invert = !!config.txinvert;
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ret_val->rx_invert = !!config.rxinvert;
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return 0;
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}
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static int lan966x_sd6g40_setup_lane(struct serdes_macro *macro,
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struct lan966x_sd6g40_setup_args config,
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u32 idx)
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{
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struct lan966x_sd6g40_setup calc_results = {};
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int ret;
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ret = lan966x_calc_sd6g40_setup_lane(macro, config, &calc_results);
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if (ret)
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return ret;
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return lan966x_sd6g40_reg_cfg(macro, &calc_results, idx);
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}
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static int lan966x_sd6g40_setup(struct serdes_macro *macro, u32 idx, int mode)
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{
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struct lan966x_sd6g40_setup_args conf = {};
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conf.refclk125M = macro->ctrl->ref125;
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if (mode == PHY_INTERFACE_MODE_QSGMII)
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conf.mode = LAN966X_SD6G40_MODE_QSGMII;
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else
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conf.mode = LAN966X_SD6G40_MODE_SGMII;
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return lan966x_sd6g40_setup_lane(macro, conf, idx);
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}
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static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct serdes_macro *macro = phy_get_drvdata(phy);
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unsigned int i;
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int val;
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/* As of now only PHY_MODE_ETHERNET is supported */
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if (mode != PHY_MODE_ETHERNET)
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return -EOPNOTSUPP;
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if (submode == PHY_INTERFACE_MODE_2500BASEX)
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macro->speed = SPEED_2500;
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else
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macro->speed = SPEED_1000;
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if (submode == PHY_INTERFACE_MODE_1000BASEX ||
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submode == PHY_INTERFACE_MODE_2500BASEX)
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submode = PHY_INTERFACE_MODE_SGMII;
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for (i = 0; i < ARRAY_SIZE(lan966x_serdes_muxes); i++) {
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if (macro->idx != lan966x_serdes_muxes[i].idx ||
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mode != lan966x_serdes_muxes[i].mode ||
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submode != lan966x_serdes_muxes[i].submode ||
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macro->port != lan966x_serdes_muxes[i].port)
|
|
continue;
|
|
|
|
val = readl(macro->ctrl->regs + lan_offset(HSIO_HW_CFG));
|
|
val |= lan966x_serdes_muxes[i].mux;
|
|
lan_rmw(val, lan966x_serdes_muxes[i].mask,
|
|
macro->ctrl->regs, HSIO_HW_CFG);
|
|
|
|
macro->mode = lan966x_serdes_muxes[i].submode;
|
|
|
|
if (macro->idx < CU_MAX)
|
|
return 0;
|
|
|
|
if (macro->idx < SERDES6G_MAX)
|
|
return lan966x_sd6g40_setup(macro,
|
|
macro->idx - (CU_MAX + 1),
|
|
macro->mode);
|
|
|
|
if (macro->idx < RGMII_MAX)
|
|
return 0;
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct phy_ops serdes_ops = {
|
|
.set_mode = serdes_set_mode,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static struct phy *serdes_simple_xlate(struct device *dev,
|
|
struct of_phandle_args *args)
|
|
{
|
|
struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
|
|
unsigned int port, idx, i;
|
|
|
|
if (args->args_count != 2)
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
port = args->args[0];
|
|
idx = args->args[1];
|
|
|
|
for (i = 0; i < SERDES_MAX; i++) {
|
|
struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
|
|
|
|
if (idx != macro->idx)
|
|
continue;
|
|
|
|
macro->port = port;
|
|
return ctrl->phys[i];
|
|
}
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
|
|
{
|
|
struct serdes_macro *macro;
|
|
|
|
*phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
|
|
if (IS_ERR(*phy))
|
|
return PTR_ERR(*phy);
|
|
|
|
macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
|
|
if (!macro)
|
|
return -ENOMEM;
|
|
|
|
macro->idx = idx;
|
|
macro->ctrl = ctrl;
|
|
macro->port = -1;
|
|
|
|
phy_set_drvdata(*phy, macro);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serdes_probe(struct platform_device *pdev)
|
|
{
|
|
struct phy_provider *provider;
|
|
struct serdes_ctrl *ctrl;
|
|
void __iomem *hw_stat;
|
|
unsigned int i;
|
|
u32 val;
|
|
int ret;
|
|
|
|
ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
|
|
if (!ctrl)
|
|
return -ENOMEM;
|
|
|
|
ctrl->dev = &pdev->dev;
|
|
ctrl->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
|
|
if (IS_ERR(ctrl->regs))
|
|
return PTR_ERR(ctrl->regs);
|
|
|
|
hw_stat = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
|
|
if (IS_ERR(hw_stat))
|
|
return PTR_ERR(hw_stat);
|
|
|
|
for (i = 0; i < SERDES_MAX; i++) {
|
|
ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
val = readl(hw_stat);
|
|
val = FIELD_GET(PLL_CONF_MASK, val);
|
|
ctrl->ref125 = (val == PLL_CONF_125MHZ ||
|
|
val == PLL_CONF_SERDES_125MHZ);
|
|
|
|
dev_set_drvdata(&pdev->dev, ctrl);
|
|
|
|
provider = devm_of_phy_provider_register(ctrl->dev,
|
|
serdes_simple_xlate);
|
|
|
|
return PTR_ERR_OR_ZERO(provider);
|
|
}
|
|
|
|
static const struct of_device_id serdes_ids[] = {
|
|
{ .compatible = "microchip,lan966x-serdes", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, serdes_ids);
|
|
|
|
static struct platform_driver mscc_lan966x_serdes = {
|
|
.probe = serdes_probe,
|
|
.driver = {
|
|
.name = "microchip,lan966x-serdes",
|
|
.of_match_table = of_match_ptr(serdes_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mscc_lan966x_serdes);
|
|
|
|
MODULE_DESCRIPTION("Microchip lan966x switch serdes driver");
|
|
MODULE_AUTHOR("Horatiu Vultur <horatiu.vultur@microchip.com>");
|
|
MODULE_LICENSE("GPL v2");
|