843 lines
26 KiB
C
843 lines
26 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright (C) 2003-2015, 2018-2022 Intel Corporation
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* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
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* Copyright (C) 2016-2017 Intel Deutschland GmbH
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*/
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#ifndef __iwl_trans_int_pcie_h__
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#define __iwl_trans_int_pcie_h__
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/skbuff.h>
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#include <linux/wait.h>
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#include <linux/pci.h>
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#include <linux/timer.h>
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#include <linux/cpu.h>
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#include "iwl-fh.h"
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#include "iwl-csr.h"
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#include "iwl-trans.h"
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#include "iwl-debug.h"
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#include "iwl-io.h"
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#include "iwl-op-mode.h"
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#include "iwl-drv.h"
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#include "queue/tx.h"
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/*
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* RX related structures and functions
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*/
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#define RX_NUM_QUEUES 1
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#define RX_POST_REQ_ALLOC 2
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#define RX_CLAIM_REQ_ALLOC 8
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#define RX_PENDING_WATERMARK 16
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#define FIRST_RX_QUEUE 512
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struct iwl_host_cmd;
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/*This file includes the declaration that are internal to the
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* trans_pcie layer */
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/**
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* struct iwl_rx_mem_buffer
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* @page_dma: bus address of rxb page
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* @page: driver's pointer to the rxb page
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* @list: list entry for the membuffer
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* @invalid: rxb is in driver ownership - not owned by HW
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* @vid: index of this rxb in the global table
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* @offset: indicates which offset of the page (in bytes)
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* this buffer uses (if multiple RBs fit into one page)
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*/
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struct iwl_rx_mem_buffer {
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dma_addr_t page_dma;
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struct page *page;
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struct list_head list;
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u32 offset;
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u16 vid;
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bool invalid;
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};
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/**
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* struct isr_statistics - interrupt statistics
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*
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*/
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struct isr_statistics {
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u32 hw;
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u32 sw;
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u32 err_code;
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u32 sch;
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u32 alive;
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u32 rfkill;
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u32 ctkill;
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u32 wakeup;
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u32 rx;
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u32 tx;
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u32 unhandled;
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};
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/**
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* struct iwl_rx_transfer_desc - transfer descriptor
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* @addr: ptr to free buffer start address
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* @rbid: unique tag of the buffer
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* @reserved: reserved
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*/
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struct iwl_rx_transfer_desc {
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__le16 rbid;
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__le16 reserved[3];
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__le64 addr;
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} __packed;
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#define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
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/**
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* struct iwl_rx_completion_desc - completion descriptor
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* @reserved1: reserved
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* @rbid: unique tag of the received buffer
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* @flags: flags (0: fragmented, all others: reserved)
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* @reserved2: reserved
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*/
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struct iwl_rx_completion_desc {
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__le32 reserved1;
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__le16 rbid;
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u8 flags;
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u8 reserved2[25];
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} __packed;
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/**
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* struct iwl_rx_completion_desc_bz - Bz completion descriptor
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* @rbid: unique tag of the received buffer
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* @flags: flags (0: fragmented, all others: reserved)
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* @reserved: reserved
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*/
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struct iwl_rx_completion_desc_bz {
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__le16 rbid;
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u8 flags;
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u8 reserved[1];
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} __packed;
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/**
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* struct iwl_rxq - Rx queue
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* @id: queue index
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* @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
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* Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
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* In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
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* @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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* @used_count: Number of RBDs handled to allocator to use for allocation
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* @write_actual:
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* @rx_free: list of RBDs with allocated RB ready for use
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* @rx_used: list of RBDs with no RB attached
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* @need_update: flag to indicate we need to update read/write index
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* @rb_stts: driver's pointer to receive buffer status
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* @rb_stts_dma: bus address of receive buffer status
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* @lock:
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* @queue: actual rx queue. Not used for multi-rx queue.
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* @next_rb_is_fragment: indicates that the previous RB that we handled set
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* the fragmented flag, so the next one is still another fragment
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*
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* NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
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*/
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struct iwl_rxq {
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int id;
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void *bd;
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dma_addr_t bd_dma;
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void *used_bd;
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dma_addr_t used_bd_dma;
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u32 read;
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u32 write;
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u32 free_count;
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u32 used_count;
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u32 write_actual;
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u32 queue_size;
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struct list_head rx_free;
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struct list_head rx_used;
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bool need_update, next_rb_is_fragment;
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void *rb_stts;
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dma_addr_t rb_stts_dma;
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spinlock_t lock;
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struct napi_struct napi;
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struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
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};
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/**
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* struct iwl_rb_allocator - Rx allocator
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* @req_pending: number of requests the allcator had not processed yet
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* @req_ready: number of requests honored and ready for claiming
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* @rbd_allocated: RBDs with pages allocated and ready to be handled to
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* the queue. This is a list of &struct iwl_rx_mem_buffer
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* @rbd_empty: RBDs with no page attached for allocator use. This is a list
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* of &struct iwl_rx_mem_buffer
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* @lock: protects the rbd_allocated and rbd_empty lists
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* @alloc_wq: work queue for background calls
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* @rx_alloc: work struct for background calls
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*/
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struct iwl_rb_allocator {
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atomic_t req_pending;
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atomic_t req_ready;
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struct list_head rbd_allocated;
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struct list_head rbd_empty;
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spinlock_t lock;
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struct workqueue_struct *alloc_wq;
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struct work_struct rx_alloc;
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};
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/**
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* iwl_get_closed_rb_stts - get closed rb stts from different structs
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* @rxq - the rxq to get the rb stts from
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*/
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static inline __le16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
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struct iwl_rxq *rxq)
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{
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
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__le16 *rb_stts = rxq->rb_stts;
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return READ_ONCE(*rb_stts);
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} else {
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struct iwl_rb_status *rb_stts = rxq->rb_stts;
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return READ_ONCE(rb_stts->closed_rb_num);
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}
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}
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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/**
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* enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
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* debugfs file
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*
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* @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
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* @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
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* @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
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* set the file can no longer be used.
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*/
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enum iwl_fw_mon_dbgfs_state {
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IWL_FW_MON_DBGFS_STATE_CLOSED,
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IWL_FW_MON_DBGFS_STATE_OPEN,
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IWL_FW_MON_DBGFS_STATE_DISABLED,
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};
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#endif
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/**
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* enum iwl_shared_irq_flags - level of sharing for irq
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* @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
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* @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
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*/
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enum iwl_shared_irq_flags {
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IWL_SHARED_IRQ_NON_RX = BIT(0),
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IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
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};
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/**
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* enum iwl_image_response_code - image response values
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* @IWL_IMAGE_RESP_DEF: the default value of the register
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* @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
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* @IWL_IMAGE_RESP_FAIL: iml reading failed
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*/
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enum iwl_image_response_code {
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IWL_IMAGE_RESP_DEF = 0,
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IWL_IMAGE_RESP_SUCCESS = 1,
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IWL_IMAGE_RESP_FAIL = 2,
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};
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/**
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* struct cont_rec: continuous recording data structure
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* @prev_wr_ptr: the last address that was read in monitor_data
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* debugfs file
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* @prev_wrap_cnt: the wrap count that was used during the last read in
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* monitor_data debugfs file
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* @state: the state of monitor_data debugfs file as described
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* in &iwl_fw_mon_dbgfs_state enum
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* @mutex: locked while reading from monitor_data debugfs file
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*/
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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struct cont_rec {
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u32 prev_wr_ptr;
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u32 prev_wrap_cnt;
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u8 state;
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/* Used to sync monitor_data debugfs file with driver unload flow */
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struct mutex mutex;
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};
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#endif
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enum iwl_pcie_fw_reset_state {
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FW_RESET_IDLE,
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FW_RESET_REQUESTED,
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FW_RESET_OK,
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FW_RESET_ERROR,
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};
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/**
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* enum wl_pcie_imr_status - imr dma transfer state
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* @IMR_D2S_IDLE: default value of the dma transfer
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* @IMR_D2S_REQUESTED: dma transfer requested
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* @IMR_D2S_COMPLETED: dma transfer completed
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* @IMR_D2S_ERROR: dma transfer error
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*/
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enum iwl_pcie_imr_status {
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IMR_D2S_IDLE,
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IMR_D2S_REQUESTED,
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IMR_D2S_COMPLETED,
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IMR_D2S_ERROR,
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};
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/**
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* struct iwl_trans_pcie - PCIe transport specific data
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* @rxq: all the RX queue data
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* @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
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* @global_table: table mapping received VID from hw to rxb
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* @rba: allocator for RX replenishing
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* @ctxt_info: context information for FW self init
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* @ctxt_info_gen3: context information for gen3 devices
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* @prph_info: prph info for self init
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* @prph_scratch: prph scratch for self init
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* @ctxt_info_dma_addr: dma addr of context information
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* @prph_info_dma_addr: dma addr of prph info
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* @prph_scratch_dma_addr: dma addr of prph scratch
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* @ctxt_info_dma_addr: dma addr of context information
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* @init_dram: DRAM data of firmware image (including paging).
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* Context information addresses will be taken from here.
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* This is driver's local copy for keeping track of size and
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* count for allocating and freeing the memory.
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* @iml: image loader image virtual address
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* @iml_dma_addr: image loader image DMA address
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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* @kw: keep warm address
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* @pnvm_dram: DRAM area that contains the PNVM data
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* @pci_dev: basic pci-network driver stuff
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* @hw_base: pci hardware address support
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* @ucode_write_complete: indicates that the ucode has been copied.
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* @ucode_write_waitq: wait queue for uCode load
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* @cmd_queue - command queue number
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* @def_rx_queue - default rx queue number
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* @rx_buf_size: Rx buffer size
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* @scd_set_active: should the transport configure the SCD for HCMD queue
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* @rx_page_order: page order for receive buffer size
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* @rx_buf_bytes: RX buffer (RB) size in bytes
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* @reg_lock: protect hw register access
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* @mutex: to protect stop_device / start_fw / start_hw
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* @cmd_in_flight: true when we have a host command in flight
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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* @fw_mon_data: fw continuous recording data
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#endif
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* @msix_entries: array of MSI-X entries
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* @msix_enabled: true if managed to enable MSI-X
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* @shared_vec_mask: the type of causes the shared vector handles
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* (see iwl_shared_irq_flags).
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* @alloc_vecs: the number of interrupt vectors allocated by the OS
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* @def_irq: default irq for non rx causes
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* @fh_init_mask: initial unmasked fh causes
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* @hw_init_mask: initial unmasked hw causes
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* @fh_mask: current unmasked fh causes
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* @hw_mask: current unmasked hw causes
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* @in_rescan: true if we have triggered a device rescan
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* @base_rb_stts: base virtual address of receive buffer status for all queues
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* @base_rb_stts_dma: base physical address of receive buffer status
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* @supported_dma_mask: DMA mask to validate the actual address against,
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* will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
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* @alloc_page_lock: spinlock for the page allocator
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* @alloc_page: allocated page to still use parts of
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* @alloc_page_used: how much of the allocated page was already used (bytes)
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* @imr_status: imr dma state machine
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* @wait_queue_head_t: imr wait queue for dma completion
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* @rf_name: name/version of the CRF, if any
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*/
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struct iwl_trans_pcie {
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struct iwl_rxq *rxq;
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struct iwl_rx_mem_buffer *rx_pool;
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struct iwl_rx_mem_buffer **global_table;
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struct iwl_rb_allocator rba;
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union {
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struct iwl_context_info *ctxt_info;
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struct iwl_context_info_gen3 *ctxt_info_gen3;
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};
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struct iwl_prph_info *prph_info;
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struct iwl_prph_scratch *prph_scratch;
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void *iml;
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dma_addr_t ctxt_info_dma_addr;
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dma_addr_t prph_info_dma_addr;
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dma_addr_t prph_scratch_dma_addr;
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dma_addr_t iml_dma_addr;
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struct iwl_trans *trans;
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struct net_device napi_dev;
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/* INT ICT Table */
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__le32 *ict_tbl;
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dma_addr_t ict_tbl_dma;
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int ict_index;
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bool use_ict;
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bool is_down, opmode_down;
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s8 debug_rfkill;
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struct isr_statistics isr_stats;
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spinlock_t irq_lock;
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struct mutex mutex;
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u32 inta_mask;
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u32 scd_base_addr;
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struct iwl_dma_ptr kw;
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struct iwl_dram_data pnvm_dram;
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struct iwl_dram_data reduce_power_dram;
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struct iwl_txq *txq_memory;
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/* PCI bus related data */
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struct pci_dev *pci_dev;
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u8 __iomem *hw_base;
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bool ucode_write_complete;
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bool sx_complete;
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wait_queue_head_t ucode_write_waitq;
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wait_queue_head_t sx_waitq;
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u8 def_rx_queue;
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u8 n_no_reclaim_cmds;
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u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
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u16 num_rx_bufs;
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enum iwl_amsdu_size rx_buf_size;
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bool scd_set_active;
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bool pcie_dbg_dumped_once;
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u32 rx_page_order;
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u32 rx_buf_bytes;
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u32 supported_dma_mask;
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/* allocator lock for the two values below */
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spinlock_t alloc_page_lock;
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struct page *alloc_page;
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u32 alloc_page_used;
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/*protect hw register */
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spinlock_t reg_lock;
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bool cmd_hold_nic_awake;
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#ifdef CONFIG_IWLWIFI_DEBUGFS
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struct cont_rec fw_mon_data;
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#endif
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struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
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bool msix_enabled;
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u8 shared_vec_mask;
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u32 alloc_vecs;
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u32 def_irq;
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u32 fh_init_mask;
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u32 hw_init_mask;
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u32 fh_mask;
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u32 hw_mask;
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cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
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u16 tx_cmd_queue_size;
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bool in_rescan;
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void *base_rb_stts;
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dma_addr_t base_rb_stts_dma;
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bool fw_reset_handshake;
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enum iwl_pcie_fw_reset_state fw_reset_state;
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wait_queue_head_t fw_reset_waitq;
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enum iwl_pcie_imr_status imr_status;
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wait_queue_head_t imr_waitq;
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char rf_name[32];
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};
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static inline struct iwl_trans_pcie *
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IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
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{
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return (void *)trans->trans_specific;
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}
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static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
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{
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/*
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* Before sending the interrupt the HW disables it to prevent
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* a nested interrupt. This is done by writing 1 to the corresponding
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* bit in the mask register. After handling the interrupt, it should be
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* re-enabled by clearing this bit. This register is defined as
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* write 1 clear (W1C) register, meaning that it's being clear
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* by writing 1 to the bit.
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*/
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iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
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}
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static inline struct iwl_trans *
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iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
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{
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return container_of((void *)trans_pcie, struct iwl_trans,
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trans_specific);
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}
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/*
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* Convention: trans API functions: iwl_trans_pcie_XXX
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* Other functions: iwl_pcie_XXX
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*/
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struct iwl_trans
|
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*iwl_trans_pcie_alloc(struct pci_dev *pdev,
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const struct pci_device_id *ent,
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const struct iwl_cfg_trans_params *cfg_trans);
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void iwl_trans_pcie_free(struct iwl_trans *trans);
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bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
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#define _iwl_trans_pcie_grab_nic_access(trans) \
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__cond_lock(nic_access_nobh, \
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likely(__iwl_trans_pcie_grab_nic_access(trans)))
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/*****************************************************
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* RX
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******************************************************/
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int iwl_pcie_rx_init(struct iwl_trans *trans);
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int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
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irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
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irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
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irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
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irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
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int iwl_pcie_rx_stop(struct iwl_trans *trans);
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void iwl_pcie_rx_free(struct iwl_trans *trans);
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void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
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void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
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void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
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struct iwl_rxq *rxq);
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/*****************************************************
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* ICT - interrupt handling
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******************************************************/
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irqreturn_t iwl_pcie_isr(int irq, void *data);
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int iwl_pcie_alloc_ict(struct iwl_trans *trans);
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void iwl_pcie_free_ict(struct iwl_trans *trans);
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void iwl_pcie_reset_ict(struct iwl_trans *trans);
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void iwl_pcie_disable_ict(struct iwl_trans *trans);
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/*****************************************************
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* TX / HCMD
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******************************************************/
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int iwl_pcie_tx_init(struct iwl_trans *trans);
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void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
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int iwl_pcie_tx_stop(struct iwl_trans *trans);
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void iwl_pcie_tx_free(struct iwl_trans *trans);
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bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
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const struct iwl_trans_txq_scd_cfg *cfg,
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unsigned int wdg_timeout);
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
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bool configure_scd);
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void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
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bool shared_mode);
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int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_tx_cmd *dev_cmd, int txq_id);
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void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
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int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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struct iwl_rx_cmd_buffer *rxb);
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void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
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/*****************************************************
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* Error handling
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******************************************************/
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void iwl_pcie_dump_csr(struct iwl_trans *trans);
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/*****************************************************
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* Helpers
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******************************************************/
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static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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clear_bit(STATUS_INT_ENABLED, &trans->status);
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if (!trans_pcie->msix_enabled) {
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/* disable interrupts from uCode/NIC to host */
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iwl_write32(trans, CSR_INT_MASK, 0x00000000);
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/* acknowledge/clear/reset any interrupts still pending
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* from uCode or flow handler (Rx/Tx DMA) */
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iwl_write32(trans, CSR_INT, 0xffffffff);
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iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
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} else {
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/* disable all the interrupt we might use */
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iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
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trans_pcie->fh_init_mask);
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iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
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trans_pcie->hw_init_mask);
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}
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IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
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}
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static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
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int start)
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{
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int i = 0;
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while (start < fw->num_sec &&
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fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
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fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
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start++;
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i++;
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}
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return i;
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}
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static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
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{
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struct iwl_self_init_dram *dram = &trans->init_dram;
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int i;
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if (!dram->fw) {
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WARN_ON(dram->fw_cnt);
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return;
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}
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for (i = 0; i < dram->fw_cnt; i++)
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dma_free_coherent(trans->dev, dram->fw[i].size,
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dram->fw[i].block, dram->fw[i].physical);
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kfree(dram->fw);
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dram->fw_cnt = 0;
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dram->fw = NULL;
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}
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static inline void iwl_disable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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spin_lock_bh(&trans_pcie->irq_lock);
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_iwl_disable_interrupts(trans);
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spin_unlock_bh(&trans_pcie->irq_lock);
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}
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static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
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set_bit(STATUS_INT_ENABLED, &trans->status);
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if (!trans_pcie->msix_enabled) {
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trans_pcie->inta_mask = CSR_INI_SET_MASK;
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iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
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} else {
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/*
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* fh/hw_mask keeps all the unmasked causes.
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* Unlike msi, in msix cause is enabled when it is unset.
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*/
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trans_pcie->hw_mask = trans_pcie->hw_init_mask;
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trans_pcie->fh_mask = trans_pcie->fh_init_mask;
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iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
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~trans_pcie->fh_mask);
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iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
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~trans_pcie->hw_mask);
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}
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}
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static inline void iwl_enable_interrupts(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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spin_lock_bh(&trans_pcie->irq_lock);
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_iwl_enable_interrupts(trans);
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spin_unlock_bh(&trans_pcie->irq_lock);
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}
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static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
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trans_pcie->hw_mask = msk;
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}
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static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
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trans_pcie->fh_mask = msk;
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}
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static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
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if (!trans_pcie->msix_enabled) {
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trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
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iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
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} else {
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iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
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trans_pcie->hw_init_mask);
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iwl_enable_fh_int_msk_msix(trans,
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MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
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}
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}
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|
|
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static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans)
|
|
{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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|
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IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n");
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|
|
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if (!trans_pcie->msix_enabled) {
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|
/*
|
|
* When we'll receive the ALIVE interrupt, the ISR will call
|
|
* iwl_enable_fw_load_int_ctx_info again to set the ALIVE
|
|
* interrupt (which is not really needed anymore) but also the
|
|
* RX interrupt which will allow us to receive the ALIVE
|
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* notification (which is Rx) and continue the flow.
|
|
*/
|
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trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX;
|
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iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
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|
} else {
|
|
iwl_enable_hw_int_msk_msix(trans,
|
|
MSIX_HW_INT_CAUSES_REG_ALIVE);
|
|
/*
|
|
* Leave all the FH causes enabled to get the ALIVE
|
|
* notification.
|
|
*/
|
|
iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
|
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}
|
|
}
|
|
|
|
static inline const char *queue_name(struct device *dev,
|
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struct iwl_trans_pcie *trans_p, int i)
|
|
{
|
|
if (trans_p->shared_vec_mask) {
|
|
int vec = trans_p->shared_vec_mask &
|
|
IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
|
|
|
|
if (i == 0)
|
|
return DRV_NAME ":shared_IRQ";
|
|
|
|
return devm_kasprintf(dev, GFP_KERNEL,
|
|
DRV_NAME ":queue_%d", i + vec);
|
|
}
|
|
if (i == 0)
|
|
return DRV_NAME ":default_queue";
|
|
|
|
if (i == trans_p->alloc_vecs - 1)
|
|
return DRV_NAME ":exception";
|
|
|
|
return devm_kasprintf(dev, GFP_KERNEL,
|
|
DRV_NAME ":queue_%d", i);
|
|
}
|
|
|
|
static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
|
|
if (!trans_pcie->msix_enabled) {
|
|
trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
|
|
iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
|
|
} else {
|
|
iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
|
|
trans_pcie->fh_init_mask);
|
|
iwl_enable_hw_int_msk_msix(trans,
|
|
MSIX_HW_INT_CAUSES_REG_RF_KILL);
|
|
}
|
|
|
|
if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
|
|
/*
|
|
* On 9000-series devices this bit isn't enabled by default, so
|
|
* when we power down the device we need set the bit to allow it
|
|
* to wake up the PCI-E bus for RF-kill interrupts.
|
|
*/
|
|
iwl_set_bit(trans, CSR_GP_CNTRL,
|
|
CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
|
|
}
|
|
}
|
|
|
|
void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans);
|
|
|
|
static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
|
|
{
|
|
struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
|
|
|
|
lockdep_assert_held(&trans_pcie->mutex);
|
|
|
|
if (trans_pcie->debug_rfkill == 1)
|
|
return true;
|
|
|
|
return !(iwl_read32(trans, CSR_GP_CNTRL) &
|
|
CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
|
|
u32 reg, u32 mask, u32 value)
|
|
{
|
|
u32 v;
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUG
|
|
WARN_ON_ONCE(value & ~mask);
|
|
#endif
|
|
|
|
v = iwl_read32(trans, reg);
|
|
v &= ~mask;
|
|
v |= value;
|
|
iwl_write32(trans, reg, v);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
|
|
u32 reg, u32 mask)
|
|
{
|
|
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
|
|
}
|
|
|
|
static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
|
|
u32 reg, u32 mask)
|
|
{
|
|
__iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
|
|
}
|
|
|
|
static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
|
|
{
|
|
return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
|
|
}
|
|
|
|
void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state);
|
|
void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
|
|
|
|
#ifdef CONFIG_IWLWIFI_DEBUGFS
|
|
void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
|
|
#else
|
|
static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
|
|
#endif
|
|
|
|
void iwl_pcie_rx_allocator_work(struct work_struct *data);
|
|
|
|
/* common functions that are used by gen2 transport */
|
|
int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
|
|
void iwl_pcie_apm_config(struct iwl_trans *trans);
|
|
int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
|
|
void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
|
|
bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
|
|
void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
|
|
bool was_in_rfkill);
|
|
void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
|
|
void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
|
|
int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
|
|
struct iwl_dma_ptr *ptr, size_t size);
|
|
void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
|
|
void iwl_pcie_apply_destination(struct iwl_trans *trans);
|
|
|
|
/* common functions that are used by gen3 transport */
|
|
void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
|
|
|
|
/* transport gen 2 exported functions */
|
|
int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
|
|
const struct fw_img *fw, bool run_in_rfkill);
|
|
void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
|
|
int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans,
|
|
struct iwl_host_cmd *cmd);
|
|
void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
|
|
void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
|
|
void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
|
|
bool test, bool reset);
|
|
int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
|
|
struct iwl_host_cmd *cmd);
|
|
int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
|
|
struct iwl_host_cmd *cmd);
|
|
void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
|
|
u32 dst_addr, u64 src_addr, u32 byte_cnt);
|
|
int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
|
|
u32 dst_addr, u64 src_addr, u32 byte_cnt);
|
|
|
|
#endif /* __iwl_trans_int_pcie_h__ */
|