415 lines
10 KiB
C
415 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for the Texas Instruments DP83TC811 PHY
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*
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*/
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#include <linux/ethtool.h>
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#include <linux/etherdevice.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/phy.h>
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#include <linux/netdevice.h>
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#define DP83TC811_PHY_ID 0x2000a253
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#define DP83811_DEVADDR 0x1f
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#define MII_DP83811_SGMII_CTRL 0x09
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#define MII_DP83811_INT_STAT1 0x12
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#define MII_DP83811_INT_STAT2 0x13
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#define MII_DP83811_INT_STAT3 0x18
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#define MII_DP83811_RESET_CTRL 0x1f
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#define DP83811_HW_RESET BIT(15)
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#define DP83811_SW_RESET BIT(14)
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/* INT_STAT1 bits */
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#define DP83811_RX_ERR_HF_INT_EN BIT(0)
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#define DP83811_MS_TRAINING_INT_EN BIT(1)
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#define DP83811_ANEG_COMPLETE_INT_EN BIT(2)
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#define DP83811_ESD_EVENT_INT_EN BIT(3)
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#define DP83811_WOL_INT_EN BIT(4)
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#define DP83811_LINK_STAT_INT_EN BIT(5)
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#define DP83811_ENERGY_DET_INT_EN BIT(6)
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#define DP83811_LINK_QUAL_INT_EN BIT(7)
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/* INT_STAT2 bits */
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#define DP83811_JABBER_DET_INT_EN BIT(0)
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#define DP83811_POLARITY_INT_EN BIT(1)
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#define DP83811_SLEEP_MODE_INT_EN BIT(2)
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#define DP83811_OVERTEMP_INT_EN BIT(3)
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#define DP83811_OVERVOLTAGE_INT_EN BIT(6)
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#define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
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/* INT_STAT3 bits */
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#define DP83811_LPS_INT_EN BIT(0)
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#define DP83811_NO_FRAME_INT_EN BIT(3)
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#define DP83811_POR_DONE_INT_EN BIT(4)
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#define MII_DP83811_RXSOP1 0x04a5
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#define MII_DP83811_RXSOP2 0x04a6
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#define MII_DP83811_RXSOP3 0x04a7
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/* WoL Registers */
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#define MII_DP83811_WOL_CFG 0x04a0
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#define MII_DP83811_WOL_STAT 0x04a1
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#define MII_DP83811_WOL_DA1 0x04a2
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#define MII_DP83811_WOL_DA2 0x04a3
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#define MII_DP83811_WOL_DA3 0x04a4
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/* WoL bits */
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#define DP83811_WOL_MAGIC_EN BIT(0)
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#define DP83811_WOL_SECURE_ON BIT(5)
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#define DP83811_WOL_EN BIT(7)
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#define DP83811_WOL_INDICATION_SEL BIT(8)
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#define DP83811_WOL_CLR_INDICATION BIT(11)
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/* SGMII CTRL bits */
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#define DP83811_TDR_AUTO BIT(8)
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#define DP83811_SGMII_EN BIT(12)
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#define DP83811_SGMII_AUTO_NEG_EN BIT(13)
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#define DP83811_SGMII_TX_ERR_DIS BIT(14)
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#define DP83811_SGMII_SOFT_RESET BIT(15)
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static int dp83811_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, MII_DP83811_INT_STAT1);
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if (err < 0)
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return err;
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err = phy_read(phydev, MII_DP83811_INT_STAT2);
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if (err < 0)
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return err;
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err = phy_read(phydev, MII_DP83811_INT_STAT3);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83811_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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const u8 *mac;
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u16 value;
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if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE)) {
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mac = (const u8 *)ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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/* MAC addresses start with byte 5, but stored in mac[0].
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* 811 PHYs store bytes 4|5, 2|3, 0|1
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*/
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA1,
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(mac[1] << 8) | mac[0]);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA2,
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(mac[3] << 8) | mac[2]);
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phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_DA3,
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(mac[5] << 8) | mac[4]);
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value = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_WOL_CFG);
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if (wol->wolopts & WAKE_MAGIC)
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value |= DP83811_WOL_MAGIC_EN;
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else
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value &= ~DP83811_WOL_MAGIC_EN;
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if (wol->wolopts & WAKE_MAGICSECURE) {
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP1,
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(wol->sopass[1] << 8) | wol->sopass[0]);
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP2,
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(wol->sopass[3] << 8) | wol->sopass[2]);
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phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP3,
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(wol->sopass[5] << 8) | wol->sopass[4]);
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value |= DP83811_WOL_SECURE_ON;
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} else {
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value &= ~DP83811_WOL_SECURE_ON;
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}
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/* Clear any pending WoL interrupt */
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phy_read(phydev, MII_DP83811_INT_STAT1);
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value |= DP83811_WOL_EN | DP83811_WOL_INDICATION_SEL |
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DP83811_WOL_CLR_INDICATION;
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return phy_write_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_WOL_CFG, value);
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} else {
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return phy_clear_bits_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_WOL_CFG, DP83811_WOL_EN);
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}
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}
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static void dp83811_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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u16 sopass_val;
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int value;
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wol->supported = (WAKE_MAGIC | WAKE_MAGICSECURE);
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wol->wolopts = 0;
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value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
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if (value & DP83811_WOL_MAGIC_EN)
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wol->wolopts |= WAKE_MAGIC;
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if (value & DP83811_WOL_SECURE_ON) {
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP1);
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wol->sopass[0] = (sopass_val & 0xff);
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wol->sopass[1] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP2);
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wol->sopass[2] = (sopass_val & 0xff);
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wol->sopass[3] = (sopass_val >> 8);
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sopass_val = phy_read_mmd(phydev, DP83811_DEVADDR,
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MII_DP83811_RXSOP3);
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wol->sopass[4] = (sopass_val & 0xff);
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wol->sopass[5] = (sopass_val >> 8);
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wol->wolopts |= WAKE_MAGICSECURE;
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}
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/* WoL is not enabled so set wolopts to 0 */
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if (!(value & DP83811_WOL_EN))
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wol->wolopts = 0;
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}
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static int dp83811_config_intr(struct phy_device *phydev)
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{
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int misr_status, err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = dp83811_ack_interrupt(phydev);
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if (err)
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return err;
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misr_status = phy_read(phydev, MII_DP83811_INT_STAT1);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83811_RX_ERR_HF_INT_EN |
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DP83811_MS_TRAINING_INT_EN |
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DP83811_ANEG_COMPLETE_INT_EN |
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DP83811_ESD_EVENT_INT_EN |
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DP83811_WOL_INT_EN |
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DP83811_LINK_STAT_INT_EN |
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DP83811_ENERGY_DET_INT_EN |
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DP83811_LINK_QUAL_INT_EN);
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err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
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if (err < 0)
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return err;
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misr_status = phy_read(phydev, MII_DP83811_INT_STAT2);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83811_JABBER_DET_INT_EN |
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DP83811_POLARITY_INT_EN |
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DP83811_SLEEP_MODE_INT_EN |
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DP83811_OVERTEMP_INT_EN |
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DP83811_OVERVOLTAGE_INT_EN |
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DP83811_UNDERVOLTAGE_INT_EN);
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err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
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if (err < 0)
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return err;
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misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
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if (misr_status < 0)
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return misr_status;
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misr_status |= (DP83811_LPS_INT_EN |
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DP83811_NO_FRAME_INT_EN |
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DP83811_POR_DONE_INT_EN);
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err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
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} else {
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err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
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if (err < 0)
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return err;
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err = dp83811_ack_interrupt(phydev);
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}
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return err;
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}
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static irqreturn_t dp83811_handle_interrupt(struct phy_device *phydev)
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{
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bool trigger_machine = false;
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int irq_status;
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/* The INT_STAT registers 1, 2 and 3 are holding the interrupt status
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* in the upper half (15:8), while the lower half (7:0) is used for
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* controlling the interrupt enable state of those individual interrupt
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* sources. To determine the possible interrupt sources, just read the
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* INT_STAT* register and use it directly to know which interrupts have
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* been enabled previously or not.
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*/
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irq_status = phy_read(phydev, MII_DP83811_INT_STAT1);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
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trigger_machine = true;
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irq_status = phy_read(phydev, MII_DP83811_INT_STAT2);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
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trigger_machine = true;
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irq_status = phy_read(phydev, MII_DP83811_INT_STAT3);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (irq_status & ((irq_status & GENMASK(7, 0)) << 8))
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trigger_machine = true;
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if (!trigger_machine)
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return IRQ_NONE;
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phy_trigger_machine(phydev);
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return IRQ_HANDLED;
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}
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static int dp83811_config_aneg(struct phy_device *phydev)
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{
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int value, err;
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
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if (phydev->autoneg == AUTONEG_ENABLE) {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(DP83811_SGMII_AUTO_NEG_EN | value));
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if (err < 0)
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return err;
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} else {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(~DP83811_SGMII_AUTO_NEG_EN & value));
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if (err < 0)
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return err;
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}
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}
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return genphy_config_aneg(phydev);
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}
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static int dp83811_config_init(struct phy_device *phydev)
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{
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int value, err;
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value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(DP83811_SGMII_EN | value));
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} else {
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err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
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(~DP83811_SGMII_EN & value));
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}
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if (err < 0)
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return err;
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value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
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return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
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value);
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}
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static int dp83811_phy_reset(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, MII_DP83811_RESET_CTRL, DP83811_HW_RESET);
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if (err < 0)
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return err;
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return 0;
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}
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static int dp83811_suspend(struct phy_device *phydev)
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{
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int value;
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value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);
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if (!(value & DP83811_WOL_EN))
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genphy_suspend(phydev);
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return 0;
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}
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static int dp83811_resume(struct phy_device *phydev)
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{
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genphy_resume(phydev);
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phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
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DP83811_WOL_CLR_INDICATION);
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return 0;
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}
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static struct phy_driver dp83811_driver[] = {
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{
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.phy_id = DP83TC811_PHY_ID,
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.phy_id_mask = 0xfffffff0,
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.name = "TI DP83TC811",
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/* PHY_BASIC_FEATURES */
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.config_init = dp83811_config_init,
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.config_aneg = dp83811_config_aneg,
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.soft_reset = dp83811_phy_reset,
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.get_wol = dp83811_get_wol,
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.set_wol = dp83811_set_wol,
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.config_intr = dp83811_config_intr,
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.handle_interrupt = dp83811_handle_interrupt,
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.suspend = dp83811_suspend,
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.resume = dp83811_resume,
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},
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};
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module_phy_driver(dp83811_driver);
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static struct mdio_device_id __maybe_unused dp83811_tbl[] = {
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{ DP83TC811_PHY_ID, 0xfffffff0 },
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{ },
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};
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MODULE_DEVICE_TABLE(mdio, dp83811_tbl);
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MODULE_DESCRIPTION("Texas Instruments DP83TC811 PHY driver");
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MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
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MODULE_LICENSE("GPL");
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