575 lines
14 KiB
C
575 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*******************************************************************************
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STMMAC Ethernet Driver -- MDIO bus implementation
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Provides Bus interface for MII registers
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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Author: Carl Shaw <carl.shaw@st.com>
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Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/gpio/consumer.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mii.h>
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#include <linux/of_mdio.h>
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#include <linux/pm_runtime.h>
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#include <linux/phy.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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#include "dwxgmac2.h"
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#include "stmmac.h"
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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#define MII_DATA_MASK GENMASK(15, 0)
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/* GMAC4 defines */
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#define MII_GMAC4_GOC_SHIFT 2
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#define MII_GMAC4_REG_ADDR_SHIFT 16
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#define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
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#define MII_GMAC4_C45E BIT(1)
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/* XGMAC defines */
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#define MII_XGMAC_SADDR BIT(18)
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#define MII_XGMAC_CMD_SHIFT 16
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#define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT)
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#define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT)
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#define MII_XGMAC_BUSY BIT(22)
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#define MII_XGMAC_MAX_C22ADDR 3
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#define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
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#define MII_XGMAC_PA_SHIFT 16
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#define MII_XGMAC_DA_SHIFT 21
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static int stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
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int phyreg, u32 *hw_addr)
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{
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u32 tmp;
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/* Set port as Clause 45 */
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tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
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tmp &= ~BIT(phyaddr);
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writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
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*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff);
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*hw_addr |= (phyreg >> MII_DEVADDR_C45_SHIFT) << MII_XGMAC_DA_SHIFT;
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return 0;
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}
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static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
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int phyreg, u32 *hw_addr)
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{
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u32 tmp;
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/* HW does not support C22 addr >= 4 */
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if (phyaddr > MII_XGMAC_MAX_C22ADDR)
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return -ENODEV;
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/* Set port as Clause 22 */
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tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
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tmp &= ~MII_XGMAC_C22P_MASK;
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tmp |= BIT(phyaddr);
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writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
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*hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f);
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return 0;
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}
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static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 tmp, addr, value = MII_XGMAC_BUSY;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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if (phyreg & MII_ADDR_C45) {
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phyreg &= ~MII_ADDR_C45;
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ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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goto err_disable_clks;
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} else {
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ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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goto err_disable_clks;
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value |= MII_XGMAC_SADDR;
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}
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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value |= MII_XGMAC_READ;
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to read */
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writel(addr, priv->ioaddr + mii_address);
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writel(value, priv->ioaddr + mii_data);
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Read the data from the MII data register */
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ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
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static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
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int phyreg, u16 phydata)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 addr, tmp, value = MII_XGMAC_BUSY;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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if (phyreg & MII_ADDR_C45) {
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phyreg &= ~MII_ADDR_C45;
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ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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goto err_disable_clks;
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} else {
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ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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goto err_disable_clks;
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value |= MII_XGMAC_SADDR;
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}
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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value |= phydata;
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value |= MII_XGMAC_WRITE;
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to write */
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writel(addr, priv->ioaddr + mii_address);
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writel(value, priv->ioaddr + mii_data);
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/* Wait until any existing MII operation is complete */
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ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
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/**
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* stmmac_mdio_read
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr
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* @phyreg: MII reg
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* Description: it reads data from the MII register from within the phy device.
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* For the 7111 GMAC, we must set the bit 0 in the MII address register while
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* accessing the PHY registers.
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* Fortunately, it seems this has no drawback for the 7109 MAC.
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*/
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static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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u32 value = MII_BUSY;
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int data = 0;
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u32 v;
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data = pm_runtime_get_sync(priv->device);
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if (data < 0) {
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pm_runtime_put_noidle(priv->device);
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return data;
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}
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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if (priv->plat->has_gmac4) {
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value |= MII_GMAC4_READ;
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if (phyreg & MII_ADDR_C45) {
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value |= MII_GMAC4_C45E;
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value &= ~priv->hw->mii.reg_mask;
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value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
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priv->hw->mii.reg_shift) &
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priv->hw->mii.reg_mask;
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data |= (phyreg & MII_REGADDR_C45_MASK) <<
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MII_GMAC4_REG_ADDR_SHIFT;
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}
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}
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000)) {
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data = -EBUSY;
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goto err_disable_clks;
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}
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000)) {
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data = -EBUSY;
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goto err_disable_clks;
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}
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/* Read the data from the MII data register */
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data = (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
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err_disable_clks:
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pm_runtime_put(priv->device);
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return data;
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}
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/**
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* stmmac_mdio_write
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* @bus: points to the mii_bus structure
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* @phyaddr: MII addr
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* @phyreg: MII reg
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* @phydata: phy data
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* Description: it writes the data into the MII register from within the device.
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*/
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static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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u16 phydata)
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{
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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int ret, data = phydata;
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u32 value = MII_BUSY;
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u32 v;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
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& priv->hw->mii.clk_csr_mask;
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if (priv->plat->has_gmac4) {
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value |= MII_GMAC4_WRITE;
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if (phyreg & MII_ADDR_C45) {
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value |= MII_GMAC4_C45E;
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value &= ~priv->hw->mii.reg_mask;
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value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) <<
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priv->hw->mii.reg_shift) &
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priv->hw->mii.reg_mask;
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data |= (phyreg & MII_REGADDR_C45_MASK) <<
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MII_GMAC4_REG_ADDR_SHIFT;
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}
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} else {
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value |= MII_WRITE;
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}
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to write */
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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/* Wait until any existing MII operation is complete */
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ret = readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
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/**
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* stmmac_mdio_reset
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* @bus: points to the mii_bus structure
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* Description: reset the MII bus
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*/
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int stmmac_mdio_reset(struct mii_bus *bus)
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{
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#if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
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struct net_device *ndev = bus->priv;
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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#ifdef CONFIG_OF
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if (priv->device->of_node) {
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struct gpio_desc *reset_gpio;
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u32 delays[3] = { 0, 0, 0 };
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reset_gpio = devm_gpiod_get_optional(priv->device,
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"snps,reset",
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GPIOD_OUT_LOW);
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if (IS_ERR(reset_gpio))
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return PTR_ERR(reset_gpio);
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device_property_read_u32_array(priv->device,
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"snps,reset-delays-us",
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delays, ARRAY_SIZE(delays));
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if (delays[0])
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msleep(DIV_ROUND_UP(delays[0], 1000));
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gpiod_set_value_cansleep(reset_gpio, 1);
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if (delays[1])
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msleep(DIV_ROUND_UP(delays[1], 1000));
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gpiod_set_value_cansleep(reset_gpio, 0);
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if (delays[2])
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msleep(DIV_ROUND_UP(delays[2], 1000));
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}
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#endif
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/* This is a workaround for problems with the STE101P PHY.
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* It doesn't complete its reset until at least one clock cycle
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* on MDC, so perform a dummy mdio read. To be updated for GMAC4
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* if needed.
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*/
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if (!priv->plat->has_gmac4)
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writel(0, priv->ioaddr + mii_address);
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#endif
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return 0;
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}
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int stmmac_xpcs_setup(struct mii_bus *bus)
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{
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struct net_device *ndev = bus->priv;
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struct mdio_device *mdiodev;
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struct stmmac_priv *priv;
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struct dw_xpcs *xpcs;
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int mode, addr;
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priv = netdev_priv(ndev);
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mode = priv->plat->phy_interface;
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/* Try to probe the XPCS by scanning all addresses. */
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for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
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mdiodev = mdio_device_create(bus, addr);
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if (IS_ERR(mdiodev))
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continue;
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xpcs = xpcs_create(mdiodev, mode);
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if (IS_ERR_OR_NULL(xpcs)) {
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mdio_device_free(mdiodev);
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continue;
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}
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priv->hw->xpcs = xpcs;
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break;
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}
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if (!priv->hw->xpcs) {
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dev_warn(priv->device, "No xPCS found\n");
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return -ENODEV;
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}
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return 0;
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}
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/**
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* stmmac_mdio_register
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* @ndev: net device structure
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* Description: it registers the MII bus
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*/
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int stmmac_mdio_register(struct net_device *ndev)
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{
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int err = 0;
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struct mii_bus *new_bus;
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
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struct device_node *mdio_node = priv->plat->mdio_node;
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struct device *dev = ndev->dev.parent;
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int addr, found, max_addr;
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if (!mdio_bus_data)
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return 0;
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new_bus = mdiobus_alloc();
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if (!new_bus)
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return -ENOMEM;
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if (mdio_bus_data->irqs)
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memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
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new_bus->name = "stmmac";
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if (priv->plat->has_gmac4)
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new_bus->probe_capabilities = MDIOBUS_C22_C45;
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if (priv->plat->has_xgmac) {
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new_bus->read = &stmmac_xgmac2_mdio_read;
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new_bus->write = &stmmac_xgmac2_mdio_write;
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/* Right now only C22 phys are supported */
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max_addr = MII_XGMAC_MAX_C22ADDR + 1;
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/* Check if DT specified an unsupported phy addr */
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if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
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dev_err(dev, "Unsupported phy_addr (max=%d)\n",
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MII_XGMAC_MAX_C22ADDR);
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} else {
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new_bus->read = &stmmac_mdio_read;
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new_bus->write = &stmmac_mdio_write;
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max_addr = PHY_MAX_ADDR;
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|
}
|
|
|
|
if (mdio_bus_data->needs_reset)
|
|
new_bus->reset = &stmmac_mdio_reset;
|
|
|
|
snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
|
|
new_bus->name, priv->plat->bus_id);
|
|
new_bus->priv = ndev;
|
|
new_bus->phy_mask = mdio_bus_data->phy_mask;
|
|
new_bus->parent = priv->device;
|
|
|
|
err = of_mdiobus_register(new_bus, mdio_node);
|
|
if (err != 0) {
|
|
dev_err(dev, "Cannot register the MDIO bus\n");
|
|
goto bus_register_fail;
|
|
}
|
|
|
|
/* Looks like we need a dummy read for XGMAC only and C45 PHYs */
|
|
if (priv->plat->has_xgmac)
|
|
stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
|
|
|
|
if (priv->plat->phy_node || mdio_node)
|
|
goto bus_register_done;
|
|
|
|
found = 0;
|
|
for (addr = 0; addr < max_addr; addr++) {
|
|
struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
|
|
|
|
if (!phydev)
|
|
continue;
|
|
|
|
/*
|
|
* If an IRQ was provided to be assigned after
|
|
* the bus probe, do it here.
|
|
*/
|
|
if (!mdio_bus_data->irqs &&
|
|
(mdio_bus_data->probed_phy_irq > 0)) {
|
|
new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
|
|
phydev->irq = mdio_bus_data->probed_phy_irq;
|
|
}
|
|
|
|
/*
|
|
* If we're going to bind the MAC to this PHY bus,
|
|
* and no PHY number was provided to the MAC,
|
|
* use the one probed here.
|
|
*/
|
|
if (priv->plat->phy_addr == -1)
|
|
priv->plat->phy_addr = addr;
|
|
|
|
phy_attached_info(phydev);
|
|
found = 1;
|
|
}
|
|
|
|
if (!found && !mdio_node) {
|
|
dev_warn(dev, "No PHY found\n");
|
|
err = -ENODEV;
|
|
goto no_phy_found;
|
|
}
|
|
|
|
bus_register_done:
|
|
priv->mii = new_bus;
|
|
|
|
return 0;
|
|
|
|
no_phy_found:
|
|
mdiobus_unregister(new_bus);
|
|
bus_register_fail:
|
|
mdiobus_free(new_bus);
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* stmmac_mdio_unregister
|
|
* @ndev: net device structure
|
|
* Description: it unregisters the MII bus
|
|
*/
|
|
int stmmac_mdio_unregister(struct net_device *ndev)
|
|
{
|
|
struct stmmac_priv *priv = netdev_priv(ndev);
|
|
|
|
if (!priv->mii)
|
|
return 0;
|
|
|
|
if (priv->hw->xpcs) {
|
|
mdio_device_free(priv->hw->xpcs->mdiodev);
|
|
xpcs_destroy(priv->hw->xpcs);
|
|
}
|
|
|
|
mdiobus_unregister(priv->mii);
|
|
priv->mii->priv = NULL;
|
|
mdiobus_free(priv->mii);
|
|
priv->mii = NULL;
|
|
|
|
return 0;
|
|
}
|