578 lines
17 KiB
C
578 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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* DWC Ether MAC version 4.xx has been used for developing this code.
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*
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* This contains the functions to handle the dma.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/io.h>
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#include "dwmac4.h"
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#include "dwmac4_dma.h"
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static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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int i;
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pr_info("dwmac4: Master AXI performs %s burst length\n",
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(value & DMA_SYS_BUS_FB) ? "fixed" : "any");
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if (axi->axi_lpi_en)
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value |= DMA_AXI_EN_LPI;
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if (axi->axi_xit_frm)
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value |= DMA_AXI_LPI_XIT_FRM;
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value &= ~DMA_AXI_WR_OSR_LMT;
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value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) <<
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DMA_AXI_WR_OSR_LMT_SHIFT;
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value &= ~DMA_AXI_RD_OSR_LMT;
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value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) <<
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DMA_AXI_RD_OSR_LMT_SHIFT;
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/* Depending on the UNDEF bit the Master AXI will perform any burst
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* length according to the BLEN programmed (by default all BLEN are
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* set).
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*/
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for (i = 0; i < AXI_BLEN; i++) {
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switch (axi->axi_blen[i]) {
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case 256:
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value |= DMA_AXI_BLEN256;
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break;
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case 128:
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value |= DMA_AXI_BLEN128;
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break;
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case 64:
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value |= DMA_AXI_BLEN64;
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break;
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case 32:
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value |= DMA_AXI_BLEN32;
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break;
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case 16:
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value |= DMA_AXI_BLEN16;
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break;
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case 8:
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value |= DMA_AXI_BLEN8;
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break;
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case 4:
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value |= DMA_AXI_BLEN4;
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break;
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}
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}
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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}
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static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_rx_phy, u32 chan)
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{
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u32 value;
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u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
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value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
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value = value | (rxpbl << DMA_BUS_MODE_RPBL_SHIFT);
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writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
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if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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writel(upper_32_bits(dma_rx_phy),
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ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan));
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writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan));
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}
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static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg,
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dma_addr_t dma_tx_phy, u32 chan)
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{
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u32 value;
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u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
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value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
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value = value | (txpbl << DMA_BUS_MODE_PBL_SHIFT);
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/* Enable OSP to get best performance */
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value |= DMA_CONTROL_OSP;
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writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
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if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
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writel(upper_32_bits(dma_tx_phy),
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ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(chan));
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writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_CHAN_TX_BASE_ADDR(chan));
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}
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static void dwmac4_dma_init_channel(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, u32 chan)
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{
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u32 value;
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/* common channel control register config */
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value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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if (dma_cfg->pblx8)
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value = value | DMA_BUS_MODE_PBL;
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writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_CHAN_INTR_DEFAULT_MASK,
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ioaddr + DMA_CHAN_INTR_ENA(chan));
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}
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static void dwmac410_dma_init_channel(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, u32 chan)
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{
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u32 value;
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/* common channel control register config */
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value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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if (dma_cfg->pblx8)
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value = value | DMA_BUS_MODE_PBL;
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writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
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ioaddr + DMA_CHAN_INTR_ENA(chan));
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}
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static void dwmac4_dma_init(void __iomem *ioaddr,
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struct stmmac_dma_cfg *dma_cfg, int atds)
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{
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u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
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/* Set the Fixed burst mode */
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if (dma_cfg->fixed_burst)
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value |= DMA_SYS_BUS_FB;
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/* Mixed Burst has no effect when fb is set */
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if (dma_cfg->mixed_burst)
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value |= DMA_SYS_BUS_MB;
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if (dma_cfg->aal)
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value |= DMA_SYS_BUS_AAL;
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if (dma_cfg->eame)
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value |= DMA_SYS_BUS_EAME;
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writel(value, ioaddr + DMA_SYS_BUS_MODE);
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value = readl(ioaddr + DMA_BUS_MODE);
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if (dma_cfg->multi_msi_en) {
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value &= ~DMA_BUS_MODE_INTM_MASK;
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value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
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}
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if (dma_cfg->dche)
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value |= DMA_BUS_MODE_DCHE;
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writel(value, ioaddr + DMA_BUS_MODE);
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}
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static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
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u32 *reg_space)
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{
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reg_space[DMA_CHAN_CONTROL(channel) / 4] =
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readl(ioaddr + DMA_CHAN_CONTROL(channel));
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reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] =
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readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));
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reg_space[DMA_CHAN_RX_CONTROL(channel) / 4] =
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readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));
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reg_space[DMA_CHAN_TX_BASE_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));
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reg_space[DMA_CHAN_RX_BASE_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
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reg_space[DMA_CHAN_TX_END_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));
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reg_space[DMA_CHAN_RX_END_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));
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reg_space[DMA_CHAN_TX_RING_LEN(channel) / 4] =
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readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));
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reg_space[DMA_CHAN_RX_RING_LEN(channel) / 4] =
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readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));
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reg_space[DMA_CHAN_INTR_ENA(channel) / 4] =
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readl(ioaddr + DMA_CHAN_INTR_ENA(channel));
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reg_space[DMA_CHAN_RX_WATCHDOG(channel) / 4] =
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readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));
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reg_space[DMA_CHAN_SLOT_CTRL_STATUS(channel) / 4] =
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readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));
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reg_space[DMA_CHAN_CUR_TX_DESC(channel) / 4] =
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readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));
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reg_space[DMA_CHAN_CUR_RX_DESC(channel) / 4] =
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readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));
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reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));
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reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(channel) / 4] =
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readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));
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reg_space[DMA_CHAN_STATUS(channel) / 4] =
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readl(ioaddr + DMA_CHAN_STATUS(channel));
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}
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static void dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)
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{
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int i;
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for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
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_dwmac4_dump_dma_regs(ioaddr, i, reg_space);
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}
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static void dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue)
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{
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writel(riwt, ioaddr + DMA_CHAN_RX_WATCHDOG(queue));
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}
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static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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unsigned int rqs = fifosz / 256 - 1;
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u32 mtl_rx_op;
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mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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if (mode == SF_DMA_MODE) {
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pr_debug("GMAC: enable RX store and forward mode\n");
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mtl_rx_op |= MTL_OP_MODE_RSF;
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} else {
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pr_debug("GMAC: disable RX SF mode (threshold %d)\n", mode);
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mtl_rx_op &= ~MTL_OP_MODE_RSF;
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mtl_rx_op &= MTL_OP_MODE_RTC_MASK;
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if (mode <= 32)
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mtl_rx_op |= MTL_OP_MODE_RTC_32;
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else if (mode <= 64)
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mtl_rx_op |= MTL_OP_MODE_RTC_64;
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else if (mode <= 96)
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mtl_rx_op |= MTL_OP_MODE_RTC_96;
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else
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mtl_rx_op |= MTL_OP_MODE_RTC_128;
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}
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mtl_rx_op &= ~MTL_OP_MODE_RQS_MASK;
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mtl_rx_op |= rqs << MTL_OP_MODE_RQS_SHIFT;
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/* Enable flow control only if each channel gets 4 KiB or more FIFO and
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* only if channel is not an AVB channel.
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*/
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if ((fifosz >= 4096) && (qmode != MTL_QUEUE_AVB)) {
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unsigned int rfd, rfa;
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mtl_rx_op |= MTL_OP_MODE_EHFC;
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/* Set Threshold for Activating Flow Control to min 2 frames,
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* i.e. 1500 * 2 = 3000 bytes.
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*
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* Set Threshold for Deactivating Flow Control to min 1 frame,
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* i.e. 1500 bytes.
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*/
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switch (fifosz) {
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case 4096:
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/* This violates the above formula because of FIFO size
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* limit therefore overflow may occur in spite of this.
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*/
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rfd = 0x03; /* Full-2.5K */
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rfa = 0x01; /* Full-1.5K */
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break;
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default:
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rfd = 0x07; /* Full-4.5K */
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rfa = 0x04; /* Full-3K */
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break;
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}
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mtl_rx_op &= ~MTL_OP_MODE_RFD_MASK;
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mtl_rx_op |= rfd << MTL_OP_MODE_RFD_SHIFT;
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mtl_rx_op &= ~MTL_OP_MODE_RFA_MASK;
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mtl_rx_op |= rfa << MTL_OP_MODE_RFA_SHIFT;
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}
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writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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}
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static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
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u32 channel, int fifosz, u8 qmode)
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{
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u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
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unsigned int tqs = fifosz / 256 - 1;
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if (mode == SF_DMA_MODE) {
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pr_debug("GMAC: enable TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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mtl_tx_op |= MTL_OP_MODE_TSF;
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} else {
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pr_debug("GMAC: disabling TX SF (threshold %d)\n", mode);
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mtl_tx_op &= ~MTL_OP_MODE_TSF;
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mtl_tx_op &= MTL_OP_MODE_TTC_MASK;
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/* Set the transmit threshold */
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if (mode <= 32)
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mtl_tx_op |= MTL_OP_MODE_TTC_32;
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else if (mode <= 64)
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mtl_tx_op |= MTL_OP_MODE_TTC_64;
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else if (mode <= 96)
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mtl_tx_op |= MTL_OP_MODE_TTC_96;
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else if (mode <= 128)
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mtl_tx_op |= MTL_OP_MODE_TTC_128;
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else if (mode <= 192)
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mtl_tx_op |= MTL_OP_MODE_TTC_192;
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else if (mode <= 256)
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mtl_tx_op |= MTL_OP_MODE_TTC_256;
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else if (mode <= 384)
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mtl_tx_op |= MTL_OP_MODE_TTC_384;
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else
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mtl_tx_op |= MTL_OP_MODE_TTC_512;
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}
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/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
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* with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
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* For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
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* with reset values: TXQEN off, TQS 256 bytes.
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*
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* TXQEN must be written for multi-channel operation and TQS must
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* reflect the available fifo size per queue (total fifo size / number
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* of enabled queues).
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*/
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mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
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if (qmode != MTL_QUEUE_AVB)
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mtl_tx_op |= MTL_OP_MODE_TXQEN;
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else
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mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
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mtl_tx_op &= ~MTL_OP_MODE_TQS_MASK;
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mtl_tx_op |= tqs << MTL_OP_MODE_TQS_SHIFT;
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writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
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}
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static int dwmac4_get_hw_feature(void __iomem *ioaddr,
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struct dma_features *dma_cap)
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{
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u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);
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/* MAC HW feature0 */
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dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL);
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dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1;
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dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2;
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dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4;
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dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18;
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dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3;
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dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5;
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dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6;
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dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7;
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/* MMC */
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dma_cap->rmon = (hw_cap & GMAC_HW_FEAT_MMCSEL) >> 8;
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/* IEEE 1588-2008 */
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dma_cap->atime_stamp = (hw_cap & GMAC_HW_FEAT_TSSEL) >> 12;
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/* 802.3az - Energy-Efficient Ethernet (EEE) */
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dma_cap->eee = (hw_cap & GMAC_HW_FEAT_EEESEL) >> 13;
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/* TX and RX csum */
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dma_cap->tx_coe = (hw_cap & GMAC_HW_FEAT_TXCOSEL) >> 14;
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dma_cap->rx_coe = (hw_cap & GMAC_HW_FEAT_RXCOESEL) >> 16;
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dma_cap->vlins = (hw_cap & GMAC_HW_FEAT_SAVLANINS) >> 27;
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dma_cap->arpoffsel = (hw_cap & GMAC_HW_FEAT_ARPOFFSEL) >> 9;
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/* MAC HW feature1 */
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hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);
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dma_cap->l3l4fnum = (hw_cap & GMAC_HW_FEAT_L3L4FNUM) >> 27;
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dma_cap->hash_tb_sz = (hw_cap & GMAC_HW_HASH_TB_SZ) >> 24;
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dma_cap->av = (hw_cap & GMAC_HW_FEAT_AVSEL) >> 20;
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dma_cap->tsoen = (hw_cap & GMAC_HW_TSOEN) >> 18;
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dma_cap->sphen = (hw_cap & GMAC_HW_FEAT_SPHEN) >> 17;
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dma_cap->addr64 = (hw_cap & GMAC_HW_ADDR64) >> 14;
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switch (dma_cap->addr64) {
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case 0:
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dma_cap->addr64 = 32;
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break;
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case 1:
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dma_cap->addr64 = 40;
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break;
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case 2:
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dma_cap->addr64 = 48;
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break;
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default:
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dma_cap->addr64 = 32;
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break;
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}
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/* RX and TX FIFO sizes are encoded as log2(n / 128). Undo that by
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* shifting and store the sizes in bytes.
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*/
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dma_cap->tx_fifo_size = 128 << ((hw_cap & GMAC_HW_TXFIFOSIZE) >> 6);
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dma_cap->rx_fifo_size = 128 << ((hw_cap & GMAC_HW_RXFIFOSIZE) >> 0);
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/* MAC HW feature2 */
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hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);
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/* TX and RX number of channels */
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dma_cap->number_rx_channel =
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((hw_cap & GMAC_HW_FEAT_RXCHCNT) >> 12) + 1;
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dma_cap->number_tx_channel =
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((hw_cap & GMAC_HW_FEAT_TXCHCNT) >> 18) + 1;
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/* TX and RX number of queues */
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dma_cap->number_rx_queues =
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((hw_cap & GMAC_HW_FEAT_RXQCNT) >> 0) + 1;
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dma_cap->number_tx_queues =
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((hw_cap & GMAC_HW_FEAT_TXQCNT) >> 6) + 1;
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/* PPS output */
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dma_cap->pps_out_num = (hw_cap & GMAC_HW_FEAT_PPSOUTNUM) >> 24;
|
|
|
|
/* IEEE 1588-2002 */
|
|
dma_cap->time_stamp = 0;
|
|
/* Number of Auxiliary Snapshot Inputs */
|
|
dma_cap->aux_snapshot_n = (hw_cap & GMAC_HW_FEAT_AUXSNAPNUM) >> 28;
|
|
|
|
/* MAC HW feature3 */
|
|
hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);
|
|
|
|
/* 5.10 Features */
|
|
dma_cap->asp = (hw_cap & GMAC_HW_FEAT_ASP) >> 28;
|
|
dma_cap->tbssel = (hw_cap & GMAC_HW_FEAT_TBSSEL) >> 27;
|
|
dma_cap->fpesel = (hw_cap & GMAC_HW_FEAT_FPESEL) >> 26;
|
|
dma_cap->estwid = (hw_cap & GMAC_HW_FEAT_ESTWID) >> 20;
|
|
dma_cap->estdep = (hw_cap & GMAC_HW_FEAT_ESTDEP) >> 17;
|
|
dma_cap->estsel = (hw_cap & GMAC_HW_FEAT_ESTSEL) >> 16;
|
|
dma_cap->frpes = (hw_cap & GMAC_HW_FEAT_FRPES) >> 13;
|
|
dma_cap->frpbs = (hw_cap & GMAC_HW_FEAT_FRPBS) >> 11;
|
|
dma_cap->frpsel = (hw_cap & GMAC_HW_FEAT_FRPSEL) >> 10;
|
|
dma_cap->dvlan = (hw_cap & GMAC_HW_FEAT_DVLAN) >> 5;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Enable/disable TSO feature and set MSS */
|
|
static void dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan)
|
|
{
|
|
u32 value;
|
|
|
|
if (en) {
|
|
/* enable TSO */
|
|
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
writel(value | DMA_CONTROL_TSE,
|
|
ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
} else {
|
|
/* enable TSO */
|
|
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
writel(value & ~DMA_CONTROL_TSE,
|
|
ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
}
|
|
}
|
|
|
|
static void dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode)
|
|
{
|
|
u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));
|
|
|
|
mtl_tx_op &= ~MTL_OP_MODE_TXQEN_MASK;
|
|
if (qmode != MTL_QUEUE_AVB)
|
|
mtl_tx_op |= MTL_OP_MODE_TXQEN;
|
|
else
|
|
mtl_tx_op |= MTL_OP_MODE_TXQEN_AV;
|
|
|
|
writel(mtl_tx_op, ioaddr + MTL_CHAN_TX_OP_MODE(channel));
|
|
}
|
|
|
|
static void dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan)
|
|
{
|
|
u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));
|
|
|
|
value &= ~DMA_RBSZ_MASK;
|
|
value |= (bfsize << DMA_RBSZ_SHIFT) & DMA_RBSZ_MASK;
|
|
|
|
writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan));
|
|
}
|
|
|
|
static void dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan)
|
|
{
|
|
u32 value = readl(ioaddr + GMAC_EXT_CONFIG);
|
|
|
|
value &= ~GMAC_CONFIG_HDSMS;
|
|
value |= GMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */
|
|
writel(value, ioaddr + GMAC_EXT_CONFIG);
|
|
|
|
value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
|
|
if (en)
|
|
value |= DMA_CONTROL_SPH;
|
|
else
|
|
value &= ~DMA_CONTROL_SPH;
|
|
writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
|
|
}
|
|
|
|
static int dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan)
|
|
{
|
|
u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
|
|
if (en)
|
|
value |= DMA_CONTROL_EDSE;
|
|
else
|
|
value &= ~DMA_CONTROL_EDSE;
|
|
|
|
writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
|
|
|
|
value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)) & DMA_CONTROL_EDSE;
|
|
if (en && !value)
|
|
return -EIO;
|
|
|
|
writel(DMA_TBS_DEF_FTOS, ioaddr + DMA_TBS_CTRL);
|
|
return 0;
|
|
}
|
|
|
|
const struct stmmac_dma_ops dwmac4_dma_ops = {
|
|
.reset = dwmac4_dma_reset,
|
|
.init = dwmac4_dma_init,
|
|
.init_chan = dwmac4_dma_init_channel,
|
|
.init_rx_chan = dwmac4_dma_init_rx_chan,
|
|
.init_tx_chan = dwmac4_dma_init_tx_chan,
|
|
.axi = dwmac4_dma_axi,
|
|
.dump_regs = dwmac4_dump_dma_regs,
|
|
.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
|
|
.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
|
|
.enable_dma_irq = dwmac4_enable_dma_irq,
|
|
.disable_dma_irq = dwmac4_disable_dma_irq,
|
|
.start_tx = dwmac4_dma_start_tx,
|
|
.stop_tx = dwmac4_dma_stop_tx,
|
|
.start_rx = dwmac4_dma_start_rx,
|
|
.stop_rx = dwmac4_dma_stop_rx,
|
|
.dma_interrupt = dwmac4_dma_interrupt,
|
|
.get_hw_feature = dwmac4_get_hw_feature,
|
|
.rx_watchdog = dwmac4_rx_watchdog,
|
|
.set_rx_ring_len = dwmac4_set_rx_ring_len,
|
|
.set_tx_ring_len = dwmac4_set_tx_ring_len,
|
|
.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
|
|
.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
|
|
.enable_tso = dwmac4_enable_tso,
|
|
.qmode = dwmac4_qmode,
|
|
.set_bfsize = dwmac4_set_bfsize,
|
|
.enable_sph = dwmac4_enable_sph,
|
|
};
|
|
|
|
const struct stmmac_dma_ops dwmac410_dma_ops = {
|
|
.reset = dwmac4_dma_reset,
|
|
.init = dwmac4_dma_init,
|
|
.init_chan = dwmac410_dma_init_channel,
|
|
.init_rx_chan = dwmac4_dma_init_rx_chan,
|
|
.init_tx_chan = dwmac4_dma_init_tx_chan,
|
|
.axi = dwmac4_dma_axi,
|
|
.dump_regs = dwmac4_dump_dma_regs,
|
|
.dma_rx_mode = dwmac4_dma_rx_chan_op_mode,
|
|
.dma_tx_mode = dwmac4_dma_tx_chan_op_mode,
|
|
.enable_dma_irq = dwmac410_enable_dma_irq,
|
|
.disable_dma_irq = dwmac4_disable_dma_irq,
|
|
.start_tx = dwmac4_dma_start_tx,
|
|
.stop_tx = dwmac4_dma_stop_tx,
|
|
.start_rx = dwmac4_dma_start_rx,
|
|
.stop_rx = dwmac4_dma_stop_rx,
|
|
.dma_interrupt = dwmac4_dma_interrupt,
|
|
.get_hw_feature = dwmac4_get_hw_feature,
|
|
.rx_watchdog = dwmac4_rx_watchdog,
|
|
.set_rx_ring_len = dwmac4_set_rx_ring_len,
|
|
.set_tx_ring_len = dwmac4_set_tx_ring_len,
|
|
.set_rx_tail_ptr = dwmac4_set_rx_tail_ptr,
|
|
.set_tx_tail_ptr = dwmac4_set_tx_tail_ptr,
|
|
.enable_tso = dwmac4_enable_tso,
|
|
.qmode = dwmac4_qmode,
|
|
.set_bfsize = dwmac4_set_bfsize,
|
|
.enable_sph = dwmac4_enable_sph,
|
|
.enable_tbs = dwmac4_enable_tbs,
|
|
};
|