478 lines
12 KiB
C
478 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#ifndef _QED_SP_H
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#define _QED_SP_H
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/qed/qed_chain.h>
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#include "qed.h"
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#include "qed_hsi.h"
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enum spq_mode {
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QED_SPQ_MODE_BLOCK, /* Client will poll a designated mem. address */
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QED_SPQ_MODE_CB, /* Client supplies a callback */
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QED_SPQ_MODE_EBLOCK, /* QED should block until completion */
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};
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struct qed_spq_comp_cb {
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void (*function)(struct qed_hwfn *p_hwfn,
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void *cookie,
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union event_ring_data *data,
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u8 fw_return_code);
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void *cookie;
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};
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/**
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* qed_eth_cqe_completion(): handles the completion of a
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* ramrod on the cqe ring.
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*
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* @p_hwfn: HW device data.
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* @cqe: CQE.
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*
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* Return: Int.
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*/
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int qed_eth_cqe_completion(struct qed_hwfn *p_hwfn,
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struct eth_slow_path_rx_cqe *cqe);
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/* QED Slow-hwfn queue interface */
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union ramrod_data {
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struct pf_start_ramrod_data pf_start;
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struct pf_update_ramrod_data pf_update;
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struct rx_queue_start_ramrod_data rx_queue_start;
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struct rx_queue_update_ramrod_data rx_queue_update;
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struct rx_queue_stop_ramrod_data rx_queue_stop;
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struct tx_queue_start_ramrod_data tx_queue_start;
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struct tx_queue_stop_ramrod_data tx_queue_stop;
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struct vport_start_ramrod_data vport_start;
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struct vport_stop_ramrod_data vport_stop;
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struct rx_update_gft_filter_ramrod_data rx_update_gft;
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struct vport_update_ramrod_data vport_update;
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struct core_rx_start_ramrod_data core_rx_queue_start;
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struct core_rx_stop_ramrod_data core_rx_queue_stop;
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struct core_tx_start_ramrod_data core_tx_queue_start;
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struct core_tx_stop_ramrod_data core_tx_queue_stop;
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struct vport_filter_update_ramrod_data vport_filter_update;
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struct rdma_init_func_ramrod_data rdma_init_func;
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struct rdma_close_func_ramrod_data rdma_close_func;
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struct rdma_register_tid_ramrod_data rdma_register_tid;
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struct rdma_deregister_tid_ramrod_data rdma_deregister_tid;
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struct roce_create_qp_resp_ramrod_data roce_create_qp_resp;
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struct roce_create_qp_req_ramrod_data roce_create_qp_req;
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struct roce_modify_qp_resp_ramrod_data roce_modify_qp_resp;
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struct roce_modify_qp_req_ramrod_data roce_modify_qp_req;
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struct roce_query_qp_resp_ramrod_data roce_query_qp_resp;
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struct roce_query_qp_req_ramrod_data roce_query_qp_req;
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struct roce_destroy_qp_resp_ramrod_data roce_destroy_qp_resp;
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struct roce_destroy_qp_req_ramrod_data roce_destroy_qp_req;
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struct roce_init_func_ramrod_data roce_init_func;
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struct rdma_create_cq_ramrod_data rdma_create_cq;
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struct rdma_destroy_cq_ramrod_data rdma_destroy_cq;
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struct rdma_srq_create_ramrod_data rdma_create_srq;
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struct rdma_srq_destroy_ramrod_data rdma_destroy_srq;
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struct rdma_srq_modify_ramrod_data rdma_modify_srq;
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struct iwarp_create_qp_ramrod_data iwarp_create_qp;
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struct iwarp_tcp_offload_ramrod_data iwarp_tcp_offload;
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struct iwarp_mpa_offload_ramrod_data iwarp_mpa_offload;
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struct iwarp_modify_qp_ramrod_data iwarp_modify_qp;
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struct iwarp_init_func_ramrod_data iwarp_init_func;
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struct fcoe_init_ramrod_params fcoe_init;
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struct fcoe_conn_offload_ramrod_params fcoe_conn_ofld;
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struct fcoe_conn_terminate_ramrod_params fcoe_conn_terminate;
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struct fcoe_stat_ramrod_params fcoe_stat;
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struct iscsi_init_ramrod_params iscsi_init;
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struct iscsi_spe_conn_offload iscsi_conn_offload;
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struct iscsi_conn_update_ramrod_params iscsi_conn_update;
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struct iscsi_spe_conn_mac_update iscsi_conn_mac_update;
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struct iscsi_spe_conn_termination iscsi_conn_terminate;
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struct nvmetcp_init_ramrod_params nvmetcp_init;
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struct nvmetcp_spe_conn_offload nvmetcp_conn_offload;
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struct nvmetcp_conn_update_ramrod_params nvmetcp_conn_update;
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struct nvmetcp_spe_conn_termination nvmetcp_conn_terminate;
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struct vf_start_ramrod_data vf_start;
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struct vf_stop_ramrod_data vf_stop;
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};
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#define EQ_MAX_CREDIT 0xffffffff
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enum spq_priority {
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QED_SPQ_PRIORITY_NORMAL,
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QED_SPQ_PRIORITY_HIGH,
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};
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union qed_spq_req_comp {
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struct qed_spq_comp_cb cb;
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u64 *done_addr;
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};
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struct qed_spq_comp_done {
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unsigned int done;
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u8 fw_return_code;
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};
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struct qed_spq_entry {
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struct list_head list;
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u8 flags;
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/* HSI slow path element */
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struct slow_path_element elem;
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union ramrod_data ramrod;
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enum spq_priority priority;
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/* pending queue for this entry */
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struct list_head *queue;
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enum spq_mode comp_mode;
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struct qed_spq_comp_cb comp_cb;
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struct qed_spq_comp_done comp_done; /* SPQ_MODE_EBLOCK */
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/* Posted entry for unlimited list entry in EBLOCK mode */
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struct qed_spq_entry *post_ent;
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};
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struct qed_eq {
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struct qed_chain chain;
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u8 eq_sb_index; /* index within the SB */
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__le16 *p_fw_cons; /* ptr to index value */
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};
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struct qed_consq {
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struct qed_chain chain;
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};
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typedef int (*qed_spq_async_comp_cb)(struct qed_hwfn *p_hwfn, u8 opcode,
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__le16 echo, union event_ring_data *data,
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u8 fw_return_code);
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int
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qed_spq_register_async_cb(struct qed_hwfn *p_hwfn,
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enum protocol_type protocol_id,
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qed_spq_async_comp_cb cb);
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void
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qed_spq_unregister_async_cb(struct qed_hwfn *p_hwfn,
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enum protocol_type protocol_id);
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struct qed_spq {
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spinlock_t lock; /* SPQ lock */
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struct list_head unlimited_pending;
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struct list_head pending;
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struct list_head completion_pending;
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struct list_head free_pool;
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struct qed_chain chain;
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/* allocated dma-able memory for spq entries (+ramrod data) */
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dma_addr_t p_phys;
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struct qed_spq_entry *p_virt;
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#define SPQ_RING_SIZE \
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(CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element))
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/* Bitmap for handling out-of-order completions */
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DECLARE_BITMAP(p_comp_bitmap, SPQ_RING_SIZE);
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u8 comp_bitmap_idx;
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/* Statistics */
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u32 unlimited_pending_count;
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u32 normal_count;
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u32 high_count;
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u32 comp_sent_count;
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u32 comp_count;
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u32 cid;
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u32 db_addr_offset;
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struct core_db_data db_data;
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qed_spq_async_comp_cb async_comp_cb[MAX_PROTOCOL_TYPE];
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};
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/**
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* qed_spq_post(): Posts a Slow hwfn request to FW, or lacking that
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* Pends it to the future list.
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*
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* @p_hwfn: HW device data.
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* @p_ent: Ent.
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* @fw_return_code: Return code from firmware.
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*
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* Return: Int.
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*/
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int qed_spq_post(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry *p_ent,
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u8 *fw_return_code);
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/**
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* qed_spq_alloc(): Alloocates & initializes the SPQ and EQ.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*/
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int qed_spq_alloc(struct qed_hwfn *p_hwfn);
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/**
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* qed_spq_setup(): Reset the SPQ to its start state.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Void.
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*/
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void qed_spq_setup(struct qed_hwfn *p_hwfn);
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/**
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* qed_spq_free(): Deallocates the given SPQ struct.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Void.
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*/
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void qed_spq_free(struct qed_hwfn *p_hwfn);
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/**
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* qed_spq_get_entry(): Obtain an entrry from the spq
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* free pool list.
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*
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* @p_hwfn: HW device data.
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* @pp_ent: PP ENT.
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*
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* Return: Int.
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*/
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int
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qed_spq_get_entry(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry **pp_ent);
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/**
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* qed_spq_return_entry(): Return an entry to spq free pool list.
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*
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* @p_hwfn: HW device data.
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* @p_ent: P ENT.
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*
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* Return: Void.
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*/
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void qed_spq_return_entry(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry *p_ent);
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/**
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* qed_eq_alloc(): Allocates & initializes an EQ struct.
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*
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* @p_hwfn: HW device data.
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* @num_elem: number of elements in the eq.
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*
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* Return: Int.
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*/
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int qed_eq_alloc(struct qed_hwfn *p_hwfn, u16 num_elem);
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/**
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* qed_eq_setup(): Reset the EQ to its start state.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Void.
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*/
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void qed_eq_setup(struct qed_hwfn *p_hwfn);
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/**
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* qed_eq_free(): deallocates the given EQ struct.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Void.
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*/
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void qed_eq_free(struct qed_hwfn *p_hwfn);
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/**
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* qed_eq_prod_update(): update the FW with default EQ producer.
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*
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* @p_hwfn: HW device data.
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* @prod: Prod.
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*
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* Return: Void.
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*/
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void qed_eq_prod_update(struct qed_hwfn *p_hwfn,
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u16 prod);
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/**
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* qed_eq_completion(): Completes currently pending EQ elements.
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*
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* @p_hwfn: HW device data.
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* @cookie: Cookie.
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*
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* Return: Int.
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*/
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int qed_eq_completion(struct qed_hwfn *p_hwfn,
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void *cookie);
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/**
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* qed_spq_completion(): Completes a single event.
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*
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* @p_hwfn: HW device data.
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* @echo: echo value from cookie (used for determining completion).
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* @fw_return_code: FW return code.
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* @p_data: data from cookie (used in callback function if applicable).
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*
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* Return: Int.
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*/
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int qed_spq_completion(struct qed_hwfn *p_hwfn,
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__le16 echo,
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u8 fw_return_code,
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union event_ring_data *p_data);
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/**
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* qed_spq_get_cid(): Given p_hwfn, return cid for the hwfn's SPQ.
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*
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* @p_hwfn: HW device data.
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*
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* Return: u32 - SPQ CID.
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*/
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u32 qed_spq_get_cid(struct qed_hwfn *p_hwfn);
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/**
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* qed_consq_alloc(): Allocates & initializes an ConsQ struct.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*/
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int qed_consq_alloc(struct qed_hwfn *p_hwfn);
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/**
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* qed_consq_setup(): Reset the ConsQ to its start state.
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*
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* @p_hwfn: HW device data.
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*
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* Return Void.
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*/
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void qed_consq_setup(struct qed_hwfn *p_hwfn);
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/**
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* qed_consq_free(): deallocates the given ConsQ struct.
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*
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* @p_hwfn: HW device data.
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*
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* Return Void.
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*/
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void qed_consq_free(struct qed_hwfn *p_hwfn);
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int qed_spq_pend_post(struct qed_hwfn *p_hwfn);
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/* Slow-hwfn low-level commands (Ramrods) function definitions. */
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#define QED_SP_EQ_COMPLETION 0x01
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#define QED_SP_CQE_COMPLETION 0x02
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struct qed_sp_init_data {
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u32 cid;
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u16 opaque_fid;
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/* Information regarding operation upon sending & completion */
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enum spq_mode comp_mode;
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struct qed_spq_comp_cb *p_comp_data;
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};
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/**
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* qed_sp_destroy_request(): Returns a SPQ entry to the pool / frees the
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* entry if allocated. Should be called on in error
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* flows after initializing the SPQ entry
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* and before posting it.
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*
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* @p_hwfn: HW device data.
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* @p_ent: Ent.
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*
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* Return: Void.
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*/
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void qed_sp_destroy_request(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry *p_ent);
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int qed_sp_init_request(struct qed_hwfn *p_hwfn,
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struct qed_spq_entry **pp_ent,
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u8 cmd,
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u8 protocol,
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struct qed_sp_init_data *p_data);
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/**
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* qed_sp_pf_start(): PF Function Start Ramrod.
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*
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* @p_hwfn: HW device data.
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* @p_ptt: P_ptt.
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* @p_tunn: P_tunn.
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* @allow_npar_tx_switch: Allow NPAR TX Switch.
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*
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* Return: Int.
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*
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* This ramrod is sent to initialize a physical function (PF). It will
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* configure the function related parameters and write its completion to the
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* event ring specified in the parameters.
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*
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* Ramrods complete on the common event ring for the PF. This ring is
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* allocated by the driver on host memory and its parameters are written
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* to the internal RAM of the UStorm by the Function Start Ramrod.
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*
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*/
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int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_tunnel_info *p_tunn,
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bool allow_npar_tx_switch);
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/**
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* qed_sp_pf_update(): PF Function Update Ramrod.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*
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* This ramrod updates function-related parameters. Every parameter can be
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* updated independently, according to configuration flags.
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*/
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int qed_sp_pf_update(struct qed_hwfn *p_hwfn);
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/**
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* qed_sp_pf_update_stag(): Update firmware of new outer tag.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*/
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int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn);
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/**
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* qed_sp_pf_update_ufp(): PF ufp update Ramrod.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*/
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int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn);
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int qed_sp_pf_stop(struct qed_hwfn *p_hwfn);
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int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_tunnel_info *p_tunn,
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enum spq_mode comp_mode,
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struct qed_spq_comp_cb *p_comp_data);
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/**
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* qed_sp_heartbeat_ramrod(): Send empty Ramrod.
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*
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* @p_hwfn: HW device data.
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*
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* Return: Int.
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*/
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int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn);
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#endif
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