945 lines
28 KiB
C
945 lines
28 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2021 Google, Inc.
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*/
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include "gve.h"
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#include "gve_adminq.h"
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#include "gve_register.h"
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#define GVE_MAX_ADMINQ_RELEASE_CHECK 500
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#define GVE_ADMINQ_SLEEP_LEN 20
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#define GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK 100
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#define GVE_DEVICE_OPTION_ERROR_FMT "%s option error:\n" \
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"Expected: length=%d, feature_mask=%x.\n" \
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"Actual: length=%d, feature_mask=%x.\n"
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#define GVE_DEVICE_OPTION_TOO_BIG_FMT "Length of %s option larger than expected. Possible older version of guest driver.\n"
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static
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struct gve_device_option *gve_get_next_option(struct gve_device_descriptor *descriptor,
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struct gve_device_option *option)
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{
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void *option_end, *descriptor_end;
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option_end = (void *)(option + 1) + be16_to_cpu(option->option_length);
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descriptor_end = (void *)descriptor + be16_to_cpu(descriptor->total_length);
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return option_end > descriptor_end ? NULL : (struct gve_device_option *)option_end;
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}
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static
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void gve_parse_device_option(struct gve_priv *priv,
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struct gve_device_descriptor *device_descriptor,
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struct gve_device_option *option,
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struct gve_device_option_gqi_rda **dev_op_gqi_rda,
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struct gve_device_option_gqi_qpl **dev_op_gqi_qpl,
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struct gve_device_option_dqo_rda **dev_op_dqo_rda,
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struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
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{
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u32 req_feat_mask = be32_to_cpu(option->required_features_mask);
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u16 option_length = be16_to_cpu(option->option_length);
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u16 option_id = be16_to_cpu(option->option_id);
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/* If the length or feature mask doesn't match, continue without
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* enabling the feature.
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*/
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switch (option_id) {
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case GVE_DEV_OPT_ID_GQI_RAW_ADDRESSING:
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if (option_length != GVE_DEV_OPT_LEN_GQI_RAW_ADDRESSING ||
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req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RAW_ADDRESSING) {
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dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
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"Raw Addressing",
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GVE_DEV_OPT_LEN_GQI_RAW_ADDRESSING,
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GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RAW_ADDRESSING,
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option_length, req_feat_mask);
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break;
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}
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dev_info(&priv->pdev->dev,
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"Gqi raw addressing device option enabled.\n");
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priv->queue_format = GVE_GQI_RDA_FORMAT;
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break;
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case GVE_DEV_OPT_ID_GQI_RDA:
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if (option_length < sizeof(**dev_op_gqi_rda) ||
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req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RDA) {
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dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
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"GQI RDA", (int)sizeof(**dev_op_gqi_rda),
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GVE_DEV_OPT_REQ_FEAT_MASK_GQI_RDA,
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option_length, req_feat_mask);
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break;
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}
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if (option_length > sizeof(**dev_op_gqi_rda)) {
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dev_warn(&priv->pdev->dev,
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GVE_DEVICE_OPTION_TOO_BIG_FMT, "GQI RDA");
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}
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*dev_op_gqi_rda = (void *)(option + 1);
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break;
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case GVE_DEV_OPT_ID_GQI_QPL:
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if (option_length < sizeof(**dev_op_gqi_qpl) ||
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req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_GQI_QPL) {
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dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
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"GQI QPL", (int)sizeof(**dev_op_gqi_qpl),
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GVE_DEV_OPT_REQ_FEAT_MASK_GQI_QPL,
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option_length, req_feat_mask);
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break;
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}
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if (option_length > sizeof(**dev_op_gqi_qpl)) {
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dev_warn(&priv->pdev->dev,
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GVE_DEVICE_OPTION_TOO_BIG_FMT, "GQI QPL");
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}
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*dev_op_gqi_qpl = (void *)(option + 1);
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break;
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case GVE_DEV_OPT_ID_DQO_RDA:
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if (option_length < sizeof(**dev_op_dqo_rda) ||
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req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_DQO_RDA) {
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dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
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"DQO RDA", (int)sizeof(**dev_op_dqo_rda),
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GVE_DEV_OPT_REQ_FEAT_MASK_DQO_RDA,
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option_length, req_feat_mask);
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break;
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}
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if (option_length > sizeof(**dev_op_dqo_rda)) {
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dev_warn(&priv->pdev->dev,
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GVE_DEVICE_OPTION_TOO_BIG_FMT, "DQO RDA");
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}
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*dev_op_dqo_rda = (void *)(option + 1);
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break;
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case GVE_DEV_OPT_ID_JUMBO_FRAMES:
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if (option_length < sizeof(**dev_op_jumbo_frames) ||
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req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES) {
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dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
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"Jumbo Frames",
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(int)sizeof(**dev_op_jumbo_frames),
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GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES,
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option_length, req_feat_mask);
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break;
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}
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if (option_length > sizeof(**dev_op_jumbo_frames)) {
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dev_warn(&priv->pdev->dev,
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GVE_DEVICE_OPTION_TOO_BIG_FMT,
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"Jumbo Frames");
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}
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*dev_op_jumbo_frames = (void *)(option + 1);
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break;
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default:
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/* If we don't recognize the option just continue
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* without doing anything.
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*/
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dev_dbg(&priv->pdev->dev, "Unrecognized device option 0x%hx not enabled.\n",
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option_id);
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}
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}
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/* Process all device options for a given describe device call. */
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static int
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gve_process_device_options(struct gve_priv *priv,
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struct gve_device_descriptor *descriptor,
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struct gve_device_option_gqi_rda **dev_op_gqi_rda,
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struct gve_device_option_gqi_qpl **dev_op_gqi_qpl,
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struct gve_device_option_dqo_rda **dev_op_dqo_rda,
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struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
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{
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const int num_options = be16_to_cpu(descriptor->num_device_options);
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struct gve_device_option *dev_opt;
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int i;
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/* The options struct directly follows the device descriptor. */
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dev_opt = (void *)(descriptor + 1);
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for (i = 0; i < num_options; i++) {
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struct gve_device_option *next_opt;
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next_opt = gve_get_next_option(descriptor, dev_opt);
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if (!next_opt) {
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dev_err(&priv->dev->dev,
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"options exceed device_descriptor's total length.\n");
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return -EINVAL;
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}
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gve_parse_device_option(priv, descriptor, dev_opt,
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dev_op_gqi_rda, dev_op_gqi_qpl,
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dev_op_dqo_rda, dev_op_jumbo_frames);
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dev_opt = next_opt;
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}
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return 0;
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}
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int gve_adminq_alloc(struct device *dev, struct gve_priv *priv)
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{
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priv->adminq = dma_alloc_coherent(dev, PAGE_SIZE,
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&priv->adminq_bus_addr, GFP_KERNEL);
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if (unlikely(!priv->adminq))
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return -ENOMEM;
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priv->adminq_mask = (PAGE_SIZE / sizeof(union gve_adminq_command)) - 1;
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priv->adminq_prod_cnt = 0;
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priv->adminq_cmd_fail = 0;
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priv->adminq_timeouts = 0;
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priv->adminq_describe_device_cnt = 0;
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priv->adminq_cfg_device_resources_cnt = 0;
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priv->adminq_register_page_list_cnt = 0;
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priv->adminq_unregister_page_list_cnt = 0;
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priv->adminq_create_tx_queue_cnt = 0;
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priv->adminq_create_rx_queue_cnt = 0;
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priv->adminq_destroy_tx_queue_cnt = 0;
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priv->adminq_destroy_rx_queue_cnt = 0;
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priv->adminq_dcfg_device_resources_cnt = 0;
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priv->adminq_set_driver_parameter_cnt = 0;
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priv->adminq_report_stats_cnt = 0;
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priv->adminq_report_link_speed_cnt = 0;
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priv->adminq_get_ptype_map_cnt = 0;
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/* Setup Admin queue with the device */
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iowrite32be(priv->adminq_bus_addr / PAGE_SIZE,
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&priv->reg_bar0->adminq_pfn);
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gve_set_admin_queue_ok(priv);
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return 0;
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}
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void gve_adminq_release(struct gve_priv *priv)
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{
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int i = 0;
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/* Tell the device the adminq is leaving */
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iowrite32be(0x0, &priv->reg_bar0->adminq_pfn);
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while (ioread32be(&priv->reg_bar0->adminq_pfn)) {
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/* If this is reached the device is unrecoverable and still
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* holding memory. Continue looping to avoid memory corruption,
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* but WARN so it is visible what is going on.
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*/
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if (i == GVE_MAX_ADMINQ_RELEASE_CHECK)
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WARN(1, "Unrecoverable platform error!");
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i++;
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msleep(GVE_ADMINQ_SLEEP_LEN);
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}
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gve_clear_device_rings_ok(priv);
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gve_clear_device_resources_ok(priv);
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gve_clear_admin_queue_ok(priv);
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}
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void gve_adminq_free(struct device *dev, struct gve_priv *priv)
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{
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if (!gve_get_admin_queue_ok(priv))
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return;
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gve_adminq_release(priv);
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dma_free_coherent(dev, PAGE_SIZE, priv->adminq, priv->adminq_bus_addr);
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gve_clear_admin_queue_ok(priv);
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}
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static void gve_adminq_kick_cmd(struct gve_priv *priv, u32 prod_cnt)
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{
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iowrite32be(prod_cnt, &priv->reg_bar0->adminq_doorbell);
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}
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static bool gve_adminq_wait_for_cmd(struct gve_priv *priv, u32 prod_cnt)
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{
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int i;
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for (i = 0; i < GVE_MAX_ADMINQ_EVENT_COUNTER_CHECK; i++) {
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if (ioread32be(&priv->reg_bar0->adminq_event_counter)
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== prod_cnt)
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return true;
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msleep(GVE_ADMINQ_SLEEP_LEN);
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}
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return false;
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}
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static int gve_adminq_parse_err(struct gve_priv *priv, u32 status)
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{
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if (status != GVE_ADMINQ_COMMAND_PASSED &&
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status != GVE_ADMINQ_COMMAND_UNSET) {
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dev_err(&priv->pdev->dev, "AQ command failed with status %d\n", status);
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priv->adminq_cmd_fail++;
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}
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switch (status) {
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case GVE_ADMINQ_COMMAND_PASSED:
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return 0;
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case GVE_ADMINQ_COMMAND_UNSET:
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dev_err(&priv->pdev->dev, "parse_aq_err: err and status both unset, this should not be possible.\n");
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return -EINVAL;
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case GVE_ADMINQ_COMMAND_ERROR_ABORTED:
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case GVE_ADMINQ_COMMAND_ERROR_CANCELLED:
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case GVE_ADMINQ_COMMAND_ERROR_DATALOSS:
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case GVE_ADMINQ_COMMAND_ERROR_FAILED_PRECONDITION:
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case GVE_ADMINQ_COMMAND_ERROR_UNAVAILABLE:
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return -EAGAIN;
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case GVE_ADMINQ_COMMAND_ERROR_ALREADY_EXISTS:
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case GVE_ADMINQ_COMMAND_ERROR_INTERNAL_ERROR:
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case GVE_ADMINQ_COMMAND_ERROR_INVALID_ARGUMENT:
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case GVE_ADMINQ_COMMAND_ERROR_NOT_FOUND:
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case GVE_ADMINQ_COMMAND_ERROR_OUT_OF_RANGE:
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case GVE_ADMINQ_COMMAND_ERROR_UNKNOWN_ERROR:
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return -EINVAL;
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case GVE_ADMINQ_COMMAND_ERROR_DEADLINE_EXCEEDED:
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return -ETIME;
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case GVE_ADMINQ_COMMAND_ERROR_PERMISSION_DENIED:
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case GVE_ADMINQ_COMMAND_ERROR_UNAUTHENTICATED:
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return -EACCES;
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case GVE_ADMINQ_COMMAND_ERROR_RESOURCE_EXHAUSTED:
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return -ENOMEM;
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case GVE_ADMINQ_COMMAND_ERROR_UNIMPLEMENTED:
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return -ENOTSUPP;
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default:
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dev_err(&priv->pdev->dev, "parse_aq_err: unknown status code %d\n", status);
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return -EINVAL;
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}
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}
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/* Flushes all AQ commands currently queued and waits for them to complete.
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* If there are failures, it will return the first error.
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*/
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static int gve_adminq_kick_and_wait(struct gve_priv *priv)
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{
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int tail, head;
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int i;
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tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
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head = priv->adminq_prod_cnt;
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gve_adminq_kick_cmd(priv, head);
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if (!gve_adminq_wait_for_cmd(priv, head)) {
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dev_err(&priv->pdev->dev, "AQ commands timed out, need to reset AQ\n");
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priv->adminq_timeouts++;
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return -ENOTRECOVERABLE;
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}
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for (i = tail; i < head; i++) {
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union gve_adminq_command *cmd;
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u32 status, err;
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cmd = &priv->adminq[i & priv->adminq_mask];
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status = be32_to_cpu(READ_ONCE(cmd->status));
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err = gve_adminq_parse_err(priv, status);
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if (err)
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// Return the first error if we failed.
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return err;
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}
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return 0;
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}
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/* This function is not threadsafe - the caller is responsible for any
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* necessary locks.
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*/
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static int gve_adminq_issue_cmd(struct gve_priv *priv,
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union gve_adminq_command *cmd_orig)
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{
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union gve_adminq_command *cmd;
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u32 opcode;
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u32 tail;
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tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
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// Check if next command will overflow the buffer.
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if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) ==
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(tail & priv->adminq_mask)) {
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int err;
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// Flush existing commands to make room.
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err = gve_adminq_kick_and_wait(priv);
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if (err)
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return err;
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// Retry.
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tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
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if (((priv->adminq_prod_cnt + 1) & priv->adminq_mask) ==
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(tail & priv->adminq_mask)) {
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// This should never happen. We just flushed the
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// command queue so there should be enough space.
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return -ENOMEM;
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}
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}
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cmd = &priv->adminq[priv->adminq_prod_cnt & priv->adminq_mask];
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priv->adminq_prod_cnt++;
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memcpy(cmd, cmd_orig, sizeof(*cmd_orig));
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opcode = be32_to_cpu(READ_ONCE(cmd->opcode));
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switch (opcode) {
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case GVE_ADMINQ_DESCRIBE_DEVICE:
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priv->adminq_describe_device_cnt++;
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break;
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case GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES:
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priv->adminq_cfg_device_resources_cnt++;
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break;
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case GVE_ADMINQ_REGISTER_PAGE_LIST:
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priv->adminq_register_page_list_cnt++;
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break;
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case GVE_ADMINQ_UNREGISTER_PAGE_LIST:
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priv->adminq_unregister_page_list_cnt++;
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break;
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case GVE_ADMINQ_CREATE_TX_QUEUE:
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priv->adminq_create_tx_queue_cnt++;
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break;
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case GVE_ADMINQ_CREATE_RX_QUEUE:
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priv->adminq_create_rx_queue_cnt++;
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break;
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case GVE_ADMINQ_DESTROY_TX_QUEUE:
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priv->adminq_destroy_tx_queue_cnt++;
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break;
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case GVE_ADMINQ_DESTROY_RX_QUEUE:
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priv->adminq_destroy_rx_queue_cnt++;
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break;
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case GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES:
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priv->adminq_dcfg_device_resources_cnt++;
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break;
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case GVE_ADMINQ_SET_DRIVER_PARAMETER:
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priv->adminq_set_driver_parameter_cnt++;
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break;
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case GVE_ADMINQ_REPORT_STATS:
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priv->adminq_report_stats_cnt++;
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break;
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case GVE_ADMINQ_REPORT_LINK_SPEED:
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priv->adminq_report_link_speed_cnt++;
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break;
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case GVE_ADMINQ_GET_PTYPE_MAP:
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priv->adminq_get_ptype_map_cnt++;
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break;
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default:
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dev_err(&priv->pdev->dev, "unknown AQ command opcode %d\n", opcode);
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}
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return 0;
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}
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/* This function is not threadsafe - the caller is responsible for any
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* necessary locks.
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* The caller is also responsible for making sure there are no commands
|
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* waiting to be executed.
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*/
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static int gve_adminq_execute_cmd(struct gve_priv *priv,
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union gve_adminq_command *cmd_orig)
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{
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u32 tail, head;
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int err;
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tail = ioread32be(&priv->reg_bar0->adminq_event_counter);
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head = priv->adminq_prod_cnt;
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if (tail != head)
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// This is not a valid path
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return -EINVAL;
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err = gve_adminq_issue_cmd(priv, cmd_orig);
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if (err)
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return err;
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return gve_adminq_kick_and_wait(priv);
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}
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/* The device specifies that the management vector can either be the first irq
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* or the last irq. ntfy_blk_msix_base_idx indicates the first irq assigned to
|
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* the ntfy blks. It if is 0 then the management vector is last, if it is 1 then
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* the management vector is first.
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*
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* gve arranges the msix vectors so that the management vector is last.
|
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*/
|
|
#define GVE_NTFY_BLK_BASE_MSIX_IDX 0
|
|
int gve_adminq_configure_device_resources(struct gve_priv *priv,
|
|
dma_addr_t counter_array_bus_addr,
|
|
u32 num_counters,
|
|
dma_addr_t db_array_bus_addr,
|
|
u32 num_ntfy_blks)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_CONFIGURE_DEVICE_RESOURCES);
|
|
cmd.configure_device_resources =
|
|
(struct gve_adminq_configure_device_resources) {
|
|
.counter_array = cpu_to_be64(counter_array_bus_addr),
|
|
.num_counters = cpu_to_be32(num_counters),
|
|
.irq_db_addr = cpu_to_be64(db_array_bus_addr),
|
|
.num_irq_dbs = cpu_to_be32(num_ntfy_blks),
|
|
.irq_db_stride = cpu_to_be32(sizeof(*priv->irq_db_indices)),
|
|
.ntfy_blk_msix_base_idx =
|
|
cpu_to_be32(GVE_NTFY_BLK_BASE_MSIX_IDX),
|
|
.queue_format = priv->queue_format,
|
|
};
|
|
|
|
return gve_adminq_execute_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_deconfigure_device_resources(struct gve_priv *priv)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_DECONFIGURE_DEVICE_RESOURCES);
|
|
|
|
return gve_adminq_execute_cmd(priv, &cmd);
|
|
}
|
|
|
|
static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index)
|
|
{
|
|
struct gve_tx_ring *tx = &priv->tx[queue_index];
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_TX_QUEUE);
|
|
cmd.create_tx_queue = (struct gve_adminq_create_tx_queue) {
|
|
.queue_id = cpu_to_be32(queue_index),
|
|
.queue_resources_addr =
|
|
cpu_to_be64(tx->q_resources_bus),
|
|
.tx_ring_addr = cpu_to_be64(tx->bus),
|
|
.ntfy_id = cpu_to_be32(tx->ntfy_id),
|
|
};
|
|
|
|
if (gve_is_gqi(priv)) {
|
|
u32 qpl_id = priv->queue_format == GVE_GQI_RDA_FORMAT ?
|
|
GVE_RAW_ADDRESSING_QPL_ID : tx->tx_fifo.qpl->id;
|
|
|
|
cmd.create_tx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
|
|
} else {
|
|
cmd.create_tx_queue.tx_ring_size =
|
|
cpu_to_be16(priv->tx_desc_cnt);
|
|
cmd.create_tx_queue.tx_comp_ring_addr =
|
|
cpu_to_be64(tx->complq_bus_dqo);
|
|
cmd.create_tx_queue.tx_comp_ring_size =
|
|
cpu_to_be16(priv->options_dqo_rda.tx_comp_ring_entries);
|
|
}
|
|
|
|
return gve_adminq_issue_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_create_tx_queues(struct gve_priv *priv, u32 num_queues)
|
|
{
|
|
int err;
|
|
int i;
|
|
|
|
for (i = 0; i < num_queues; i++) {
|
|
err = gve_adminq_create_tx_queue(priv, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return gve_adminq_kick_and_wait(priv);
|
|
}
|
|
|
|
static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
|
|
{
|
|
struct gve_rx_ring *rx = &priv->rx[queue_index];
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_CREATE_RX_QUEUE);
|
|
cmd.create_rx_queue = (struct gve_adminq_create_rx_queue) {
|
|
.queue_id = cpu_to_be32(queue_index),
|
|
.ntfy_id = cpu_to_be32(rx->ntfy_id),
|
|
.queue_resources_addr = cpu_to_be64(rx->q_resources_bus),
|
|
};
|
|
|
|
if (gve_is_gqi(priv)) {
|
|
u32 qpl_id = priv->queue_format == GVE_GQI_RDA_FORMAT ?
|
|
GVE_RAW_ADDRESSING_QPL_ID : rx->data.qpl->id;
|
|
|
|
cmd.create_rx_queue.rx_desc_ring_addr =
|
|
cpu_to_be64(rx->desc.bus),
|
|
cmd.create_rx_queue.rx_data_ring_addr =
|
|
cpu_to_be64(rx->data.data_bus),
|
|
cmd.create_rx_queue.index = cpu_to_be32(queue_index);
|
|
cmd.create_rx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
|
|
cmd.create_rx_queue.packet_buffer_size = cpu_to_be16(rx->packet_buffer_size);
|
|
} else {
|
|
cmd.create_rx_queue.rx_ring_size =
|
|
cpu_to_be16(priv->rx_desc_cnt);
|
|
cmd.create_rx_queue.rx_desc_ring_addr =
|
|
cpu_to_be64(rx->dqo.complq.bus);
|
|
cmd.create_rx_queue.rx_data_ring_addr =
|
|
cpu_to_be64(rx->dqo.bufq.bus);
|
|
cmd.create_rx_queue.packet_buffer_size =
|
|
cpu_to_be16(priv->data_buffer_size_dqo);
|
|
cmd.create_rx_queue.rx_buff_ring_size =
|
|
cpu_to_be16(priv->options_dqo_rda.rx_buff_ring_entries);
|
|
cmd.create_rx_queue.enable_rsc =
|
|
!!(priv->dev->features & NETIF_F_LRO);
|
|
}
|
|
|
|
return gve_adminq_issue_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_create_rx_queues(struct gve_priv *priv, u32 num_queues)
|
|
{
|
|
int err;
|
|
int i;
|
|
|
|
for (i = 0; i < num_queues; i++) {
|
|
err = gve_adminq_create_rx_queue(priv, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return gve_adminq_kick_and_wait(priv);
|
|
}
|
|
|
|
static int gve_adminq_destroy_tx_queue(struct gve_priv *priv, u32 queue_index)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
int err;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_TX_QUEUE);
|
|
cmd.destroy_tx_queue = (struct gve_adminq_destroy_tx_queue) {
|
|
.queue_id = cpu_to_be32(queue_index),
|
|
};
|
|
|
|
err = gve_adminq_issue_cmd(priv, &cmd);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int gve_adminq_destroy_tx_queues(struct gve_priv *priv, u32 num_queues)
|
|
{
|
|
int err;
|
|
int i;
|
|
|
|
for (i = 0; i < num_queues; i++) {
|
|
err = gve_adminq_destroy_tx_queue(priv, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return gve_adminq_kick_and_wait(priv);
|
|
}
|
|
|
|
static int gve_adminq_destroy_rx_queue(struct gve_priv *priv, u32 queue_index)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
int err;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESTROY_RX_QUEUE);
|
|
cmd.destroy_rx_queue = (struct gve_adminq_destroy_rx_queue) {
|
|
.queue_id = cpu_to_be32(queue_index),
|
|
};
|
|
|
|
err = gve_adminq_issue_cmd(priv, &cmd);
|
|
if (err)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int gve_adminq_destroy_rx_queues(struct gve_priv *priv, u32 num_queues)
|
|
{
|
|
int err;
|
|
int i;
|
|
|
|
for (i = 0; i < num_queues; i++) {
|
|
err = gve_adminq_destroy_rx_queue(priv, i);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return gve_adminq_kick_and_wait(priv);
|
|
}
|
|
|
|
static int gve_set_desc_cnt(struct gve_priv *priv,
|
|
struct gve_device_descriptor *descriptor)
|
|
{
|
|
priv->tx_desc_cnt = be16_to_cpu(descriptor->tx_queue_entries);
|
|
if (priv->tx_desc_cnt * sizeof(priv->tx->desc[0]) < PAGE_SIZE) {
|
|
dev_err(&priv->pdev->dev, "Tx desc count %d too low\n",
|
|
priv->tx_desc_cnt);
|
|
return -EINVAL;
|
|
}
|
|
priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
|
|
if (priv->rx_desc_cnt * sizeof(priv->rx->desc.desc_ring[0])
|
|
< PAGE_SIZE) {
|
|
dev_err(&priv->pdev->dev, "Rx desc count %d too low\n",
|
|
priv->rx_desc_cnt);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
gve_set_desc_cnt_dqo(struct gve_priv *priv,
|
|
const struct gve_device_descriptor *descriptor,
|
|
const struct gve_device_option_dqo_rda *dev_op_dqo_rda)
|
|
{
|
|
priv->tx_desc_cnt = be16_to_cpu(descriptor->tx_queue_entries);
|
|
priv->options_dqo_rda.tx_comp_ring_entries =
|
|
be16_to_cpu(dev_op_dqo_rda->tx_comp_ring_entries);
|
|
priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
|
|
priv->options_dqo_rda.rx_buff_ring_entries =
|
|
be16_to_cpu(dev_op_dqo_rda->rx_buff_ring_entries);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gve_enable_supported_features(struct gve_priv *priv,
|
|
u32 supported_features_mask,
|
|
const struct gve_device_option_jumbo_frames
|
|
*dev_op_jumbo_frames)
|
|
{
|
|
/* Before control reaches this point, the page-size-capped max MTU from
|
|
* the gve_device_descriptor field has already been stored in
|
|
* priv->dev->max_mtu. We overwrite it with the true max MTU below.
|
|
*/
|
|
if (dev_op_jumbo_frames &&
|
|
(supported_features_mask & GVE_SUP_JUMBO_FRAMES_MASK)) {
|
|
dev_info(&priv->pdev->dev,
|
|
"JUMBO FRAMES device option enabled.\n");
|
|
priv->dev->max_mtu = be16_to_cpu(dev_op_jumbo_frames->max_mtu);
|
|
}
|
|
}
|
|
|
|
int gve_adminq_describe_device(struct gve_priv *priv)
|
|
{
|
|
struct gve_device_option_jumbo_frames *dev_op_jumbo_frames = NULL;
|
|
struct gve_device_option_gqi_rda *dev_op_gqi_rda = NULL;
|
|
struct gve_device_option_gqi_qpl *dev_op_gqi_qpl = NULL;
|
|
struct gve_device_option_dqo_rda *dev_op_dqo_rda = NULL;
|
|
struct gve_device_descriptor *descriptor;
|
|
u32 supported_features_mask = 0;
|
|
union gve_adminq_command cmd;
|
|
dma_addr_t descriptor_bus;
|
|
int err = 0;
|
|
u8 *mac;
|
|
u16 mtu;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
descriptor = dma_alloc_coherent(&priv->pdev->dev, PAGE_SIZE,
|
|
&descriptor_bus, GFP_KERNEL);
|
|
if (!descriptor)
|
|
return -ENOMEM;
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_DESCRIBE_DEVICE);
|
|
cmd.describe_device.device_descriptor_addr =
|
|
cpu_to_be64(descriptor_bus);
|
|
cmd.describe_device.device_descriptor_version =
|
|
cpu_to_be32(GVE_ADMINQ_DEVICE_DESCRIPTOR_VERSION);
|
|
cmd.describe_device.available_length = cpu_to_be32(PAGE_SIZE);
|
|
|
|
err = gve_adminq_execute_cmd(priv, &cmd);
|
|
if (err)
|
|
goto free_device_descriptor;
|
|
|
|
err = gve_process_device_options(priv, descriptor, &dev_op_gqi_rda,
|
|
&dev_op_gqi_qpl, &dev_op_dqo_rda,
|
|
&dev_op_jumbo_frames);
|
|
if (err)
|
|
goto free_device_descriptor;
|
|
|
|
/* If the GQI_RAW_ADDRESSING option is not enabled and the queue format
|
|
* is not set to GqiRda, choose the queue format in a priority order:
|
|
* DqoRda, GqiRda, GqiQpl. Use GqiQpl as default.
|
|
*/
|
|
if (dev_op_dqo_rda) {
|
|
priv->queue_format = GVE_DQO_RDA_FORMAT;
|
|
dev_info(&priv->pdev->dev,
|
|
"Driver is running with DQO RDA queue format.\n");
|
|
supported_features_mask =
|
|
be32_to_cpu(dev_op_dqo_rda->supported_features_mask);
|
|
} else if (dev_op_gqi_rda) {
|
|
priv->queue_format = GVE_GQI_RDA_FORMAT;
|
|
dev_info(&priv->pdev->dev,
|
|
"Driver is running with GQI RDA queue format.\n");
|
|
supported_features_mask =
|
|
be32_to_cpu(dev_op_gqi_rda->supported_features_mask);
|
|
} else if (priv->queue_format == GVE_GQI_RDA_FORMAT) {
|
|
dev_info(&priv->pdev->dev,
|
|
"Driver is running with GQI RDA queue format.\n");
|
|
} else {
|
|
priv->queue_format = GVE_GQI_QPL_FORMAT;
|
|
if (dev_op_gqi_qpl)
|
|
supported_features_mask =
|
|
be32_to_cpu(dev_op_gqi_qpl->supported_features_mask);
|
|
dev_info(&priv->pdev->dev,
|
|
"Driver is running with GQI QPL queue format.\n");
|
|
}
|
|
if (gve_is_gqi(priv)) {
|
|
err = gve_set_desc_cnt(priv, descriptor);
|
|
} else {
|
|
/* DQO supports LRO. */
|
|
priv->dev->hw_features |= NETIF_F_LRO;
|
|
err = gve_set_desc_cnt_dqo(priv, descriptor, dev_op_dqo_rda);
|
|
}
|
|
if (err)
|
|
goto free_device_descriptor;
|
|
|
|
priv->max_registered_pages =
|
|
be64_to_cpu(descriptor->max_registered_pages);
|
|
mtu = be16_to_cpu(descriptor->mtu);
|
|
if (mtu < ETH_MIN_MTU) {
|
|
dev_err(&priv->pdev->dev, "MTU %d below minimum MTU\n", mtu);
|
|
err = -EINVAL;
|
|
goto free_device_descriptor;
|
|
}
|
|
priv->dev->max_mtu = mtu;
|
|
priv->num_event_counters = be16_to_cpu(descriptor->counters);
|
|
eth_hw_addr_set(priv->dev, descriptor->mac);
|
|
mac = descriptor->mac;
|
|
dev_info(&priv->pdev->dev, "MAC addr: %pM\n", mac);
|
|
priv->tx_pages_per_qpl = be16_to_cpu(descriptor->tx_pages_per_qpl);
|
|
priv->rx_data_slot_cnt = be16_to_cpu(descriptor->rx_pages_per_qpl);
|
|
|
|
if (gve_is_gqi(priv) && priv->rx_data_slot_cnt < priv->rx_desc_cnt) {
|
|
dev_err(&priv->pdev->dev, "rx_data_slot_cnt cannot be smaller than rx_desc_cnt, setting rx_desc_cnt down to %d.\n",
|
|
priv->rx_data_slot_cnt);
|
|
priv->rx_desc_cnt = priv->rx_data_slot_cnt;
|
|
}
|
|
priv->default_num_queues = be16_to_cpu(descriptor->default_num_queues);
|
|
|
|
gve_enable_supported_features(priv, supported_features_mask,
|
|
dev_op_jumbo_frames);
|
|
|
|
free_device_descriptor:
|
|
dma_free_coherent(&priv->pdev->dev, PAGE_SIZE, descriptor,
|
|
descriptor_bus);
|
|
return err;
|
|
}
|
|
|
|
int gve_adminq_register_page_list(struct gve_priv *priv,
|
|
struct gve_queue_page_list *qpl)
|
|
{
|
|
struct device *hdev = &priv->pdev->dev;
|
|
u32 num_entries = qpl->num_entries;
|
|
u32 size = num_entries * sizeof(qpl->page_buses[0]);
|
|
union gve_adminq_command cmd;
|
|
dma_addr_t page_list_bus;
|
|
__be64 *page_list;
|
|
int err;
|
|
int i;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
page_list = dma_alloc_coherent(hdev, size, &page_list_bus, GFP_KERNEL);
|
|
if (!page_list)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < num_entries; i++)
|
|
page_list[i] = cpu_to_be64(qpl->page_buses[i]);
|
|
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_REGISTER_PAGE_LIST);
|
|
cmd.reg_page_list = (struct gve_adminq_register_page_list) {
|
|
.page_list_id = cpu_to_be32(qpl->id),
|
|
.num_pages = cpu_to_be32(num_entries),
|
|
.page_address_list_addr = cpu_to_be64(page_list_bus),
|
|
};
|
|
|
|
err = gve_adminq_execute_cmd(priv, &cmd);
|
|
dma_free_coherent(hdev, size, page_list, page_list_bus);
|
|
return err;
|
|
}
|
|
|
|
int gve_adminq_unregister_page_list(struct gve_priv *priv, u32 page_list_id)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_UNREGISTER_PAGE_LIST);
|
|
cmd.unreg_page_list = (struct gve_adminq_unregister_page_list) {
|
|
.page_list_id = cpu_to_be32(page_list_id),
|
|
};
|
|
|
|
return gve_adminq_execute_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_set_mtu(struct gve_priv *priv, u64 mtu)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_SET_DRIVER_PARAMETER);
|
|
cmd.set_driver_param = (struct gve_adminq_set_driver_parameter) {
|
|
.parameter_type = cpu_to_be32(GVE_SET_PARAM_MTU),
|
|
.parameter_value = cpu_to_be64(mtu),
|
|
};
|
|
|
|
return gve_adminq_execute_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_report_stats(struct gve_priv *priv, u64 stats_report_len,
|
|
dma_addr_t stats_report_addr, u64 interval)
|
|
{
|
|
union gve_adminq_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_STATS);
|
|
cmd.report_stats = (struct gve_adminq_report_stats) {
|
|
.stats_report_len = cpu_to_be64(stats_report_len),
|
|
.stats_report_addr = cpu_to_be64(stats_report_addr),
|
|
.interval = cpu_to_be64(interval),
|
|
};
|
|
|
|
return gve_adminq_execute_cmd(priv, &cmd);
|
|
}
|
|
|
|
int gve_adminq_report_link_speed(struct gve_priv *priv)
|
|
{
|
|
union gve_adminq_command gvnic_cmd;
|
|
dma_addr_t link_speed_region_bus;
|
|
__be64 *link_speed_region;
|
|
int err;
|
|
|
|
link_speed_region =
|
|
dma_alloc_coherent(&priv->pdev->dev, sizeof(*link_speed_region),
|
|
&link_speed_region_bus, GFP_KERNEL);
|
|
|
|
if (!link_speed_region)
|
|
return -ENOMEM;
|
|
|
|
memset(&gvnic_cmd, 0, sizeof(gvnic_cmd));
|
|
gvnic_cmd.opcode = cpu_to_be32(GVE_ADMINQ_REPORT_LINK_SPEED);
|
|
gvnic_cmd.report_link_speed.link_speed_address =
|
|
cpu_to_be64(link_speed_region_bus);
|
|
|
|
err = gve_adminq_execute_cmd(priv, &gvnic_cmd);
|
|
|
|
priv->link_speed = be64_to_cpu(*link_speed_region);
|
|
dma_free_coherent(&priv->pdev->dev, sizeof(*link_speed_region), link_speed_region,
|
|
link_speed_region_bus);
|
|
return err;
|
|
}
|
|
|
|
int gve_adminq_get_ptype_map_dqo(struct gve_priv *priv,
|
|
struct gve_ptype_lut *ptype_lut)
|
|
{
|
|
struct gve_ptype_map *ptype_map;
|
|
union gve_adminq_command cmd;
|
|
dma_addr_t ptype_map_bus;
|
|
int err = 0;
|
|
int i;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
ptype_map = dma_alloc_coherent(&priv->pdev->dev, sizeof(*ptype_map),
|
|
&ptype_map_bus, GFP_KERNEL);
|
|
if (!ptype_map)
|
|
return -ENOMEM;
|
|
|
|
cmd.opcode = cpu_to_be32(GVE_ADMINQ_GET_PTYPE_MAP);
|
|
cmd.get_ptype_map = (struct gve_adminq_get_ptype_map) {
|
|
.ptype_map_len = cpu_to_be64(sizeof(*ptype_map)),
|
|
.ptype_map_addr = cpu_to_be64(ptype_map_bus),
|
|
};
|
|
|
|
err = gve_adminq_execute_cmd(priv, &cmd);
|
|
if (err)
|
|
goto err;
|
|
|
|
/* Populate ptype_lut. */
|
|
for (i = 0; i < GVE_NUM_PTYPES; i++) {
|
|
ptype_lut->ptypes[i].l3_type =
|
|
ptype_map->ptypes[i].l3_type;
|
|
ptype_lut->ptypes[i].l4_type =
|
|
ptype_map->ptypes[i].l4_type;
|
|
}
|
|
err:
|
|
dma_free_coherent(&priv->pdev->dev, sizeof(*ptype_map), ptype_map,
|
|
ptype_map_bus);
|
|
return err;
|
|
}
|