531 lines
14 KiB
C
531 lines
14 KiB
C
/*
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* Toshiba TMIO NAND flash controller driver
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*
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* Slightly murky pre-git history of the driver:
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*
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* Copyright (c) Ian Molton 2004, 2005, 2008
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* Original work, independent of sharps code. Included hardware ECC support.
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* Hard ECC did not work for writes in the early revisions.
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* Copyright (c) Dirk Opfer 2005.
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* Modifications developed from sharps code but
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* NOT containing any, ported onto Ians base.
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* Copyright (c) Chris Humbert 2005
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* Copyright (c) Dmitry Baryshkov 2008
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* Minor fixes
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*
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* Parts copyright Sebastian Carlier
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*
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* This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/tmio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/slab.h>
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/*--------------------------------------------------------------------------*/
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/*
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* NAND Flash Host Controller Configuration Register
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*/
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#define CCR_COMMAND 0x04 /* w Command */
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#define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
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#define CCR_INTP 0x3d /* b Interrupt Pin */
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#define CCR_INTE 0x48 /* b Interrupt Enable */
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#define CCR_EC 0x4a /* b Event Control */
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#define CCR_ICC 0x4c /* b Internal Clock Control */
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#define CCR_ECCC 0x5b /* b ECC Control */
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#define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
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#define CCR_NFM 0x61 /* b NAND Flash Monitor */
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#define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
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#define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
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/*
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* NAND Flash Control Register
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*/
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#define FCR_DATA 0x00 /* bwl Data Register */
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#define FCR_MODE 0x04 /* b Mode Register */
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#define FCR_STATUS 0x05 /* b Status Register */
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#define FCR_ISR 0x06 /* b Interrupt Status Register */
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#define FCR_IMR 0x07 /* b Interrupt Mask Register */
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/* FCR_MODE Register Command List */
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#define FCR_MODE_DATA 0x94 /* Data Data_Mode */
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#define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
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#define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
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#define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
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#define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
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#define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
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#define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
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#define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
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#define FCR_MODE_LED_OFF 0x00 /* LED OFF */
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#define FCR_MODE_LED_ON 0x04 /* LED ON */
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#define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
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#define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
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#define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
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#define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
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#define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
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#define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
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#define FCR_MODE_WE 0x80
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#define FCR_MODE_ECC1 0x40
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#define FCR_MODE_ECC0 0x20
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#define FCR_MODE_CE 0x10
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#define FCR_MODE_PCNT1 0x08
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#define FCR_MODE_PCNT0 0x04
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#define FCR_MODE_ALE 0x02
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#define FCR_MODE_CLE 0x01
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#define FCR_STATUS_BUSY 0x80
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/*--------------------------------------------------------------------------*/
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struct tmio_nand {
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struct nand_controller controller;
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struct nand_chip chip;
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struct completion comp;
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struct platform_device *dev;
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void __iomem *ccr;
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void __iomem *fcr;
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unsigned long fcr_base;
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unsigned int irq;
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/* for tmio_nand_read_byte */
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u8 read;
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unsigned read_good:1;
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};
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static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
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{
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return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
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}
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/*--------------------------------------------------------------------------*/
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static void tmio_nand_hwcontrol(struct nand_chip *chip, int cmd,
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unsigned int ctrl)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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if (ctrl & NAND_CTRL_CHANGE) {
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u8 mode;
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if (ctrl & NAND_NCE) {
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mode = FCR_MODE_DATA;
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if (ctrl & NAND_CLE)
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mode |= FCR_MODE_CLE;
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else
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mode &= ~FCR_MODE_CLE;
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if (ctrl & NAND_ALE)
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mode |= FCR_MODE_ALE;
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else
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mode &= ~FCR_MODE_ALE;
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} else {
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mode = FCR_MODE_STANDBY;
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}
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tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
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tmio->read_good = 0;
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}
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if (cmd != NAND_CMD_NONE)
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tmio_iowrite8(cmd, chip->legacy.IO_ADDR_W);
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}
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static int tmio_nand_dev_ready(struct nand_chip *chip)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
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}
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static irqreturn_t tmio_irq(int irq, void *__tmio)
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{
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struct tmio_nand *tmio = __tmio;
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/* disable RDYREQ interrupt */
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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complete(&tmio->comp);
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return IRQ_HANDLED;
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}
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/*
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*The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
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*This interrupt is normally disabled, but for long operations like
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*erase and write, we enable it to wake us up. The irq handler
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*disables the interrupt.
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*/
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static int tmio_nand_wait(struct nand_chip *nand_chip)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(nand_chip));
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long timeout;
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u8 status;
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/* enable RDYREQ interrupt */
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tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
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reinit_completion(&tmio->comp);
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tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
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timeout = 400;
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timeout = wait_for_completion_timeout(&tmio->comp,
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msecs_to_jiffies(timeout));
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if (unlikely(!tmio_nand_dev_ready(nand_chip))) {
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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dev_warn(&tmio->dev->dev, "still busy after 400 ms\n");
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} else if (unlikely(!timeout)) {
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tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
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dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
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}
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nand_status_op(nand_chip, &status);
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return status;
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}
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/*
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*The TMIO controller combines two 8-bit data bytes into one 16-bit
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*word. This function separates them so nand_base.c works as expected,
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*especially its NAND_CMD_READID routines.
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*
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*To prevent stale data from being read, tmio_nand_hwcontrol() clears
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*tmio->read_good.
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*/
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static u_char tmio_nand_read_byte(struct nand_chip *chip)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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unsigned int data;
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if (tmio->read_good--)
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return tmio->read;
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data = tmio_ioread16(tmio->fcr + FCR_DATA);
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tmio->read = data >> 8;
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return data;
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}
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/*
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*The TMIO controller converts an 8-bit NAND interface to a 16-bit
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*bus interface, so all data reads and writes must be 16-bit wide.
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*Thus, we implement 16-bit versions of the read, write, and verify
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*buffer functions.
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*/
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static void
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tmio_nand_write_buf(struct nand_chip *chip, const u_char *buf, int len)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
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}
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static void tmio_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
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}
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static void tmio_nand_enable_hwecc(struct nand_chip *chip, int mode)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
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tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
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tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
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}
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static int tmio_nand_calculate_ecc(struct nand_chip *chip, const u_char *dat,
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u_char *ecc_code)
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{
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struct tmio_nand *tmio = mtd_to_tmio(nand_to_mtd(chip));
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unsigned int ecc;
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tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[1] = ecc; /* 000-255 LP7-0 */
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ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
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ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
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ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
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ecc_code[3] = ecc; /* 256-511 LP15-8 */
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ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
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tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
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return 0;
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}
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static int tmio_nand_correct_data(struct nand_chip *chip, unsigned char *buf,
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unsigned char *read_ecc,
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unsigned char *calc_ecc)
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{
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int r0, r1;
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/* assume ecc.size = 512 and ecc.bytes = 6 */
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r0 = rawnand_sw_hamming_correct(chip, buf, read_ecc, calc_ecc);
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if (r0 < 0)
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return r0;
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r1 = rawnand_sw_hamming_correct(chip, buf + 256, read_ecc + 3,
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calc_ecc + 3);
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if (r1 < 0)
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return r1;
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return r0 + r1;
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}
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static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
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{
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const struct mfd_cell *cell = mfd_get_cell(dev);
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int ret;
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if (cell->enable) {
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ret = cell->enable(dev);
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if (ret)
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return ret;
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}
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/* (4Ch) CLKRUN Enable 1st spcrunc */
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tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
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/* (10h)BaseAddress 0x1000 spba.spba2 */
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tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
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tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
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/* (04h)Command Register I/O spcmd */
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tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
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/* (62h) Power Supply Control ssmpwc */
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/* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
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tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
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/* (63h) Detect Control ssmdtc */
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tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
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/* Interrupt status register clear sintst */
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tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
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/* After power supply, Media are reset smode */
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tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
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tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
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tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
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/* Standby Mode smode */
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tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
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mdelay(5);
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return 0;
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}
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static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
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{
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const struct mfd_cell *cell = mfd_get_cell(dev);
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tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
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if (cell->disable)
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cell->disable(dev);
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}
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static int tmio_attach_chip(struct nand_chip *chip)
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{
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if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
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return 0;
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chip->ecc.size = 512;
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chip->ecc.bytes = 6;
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chip->ecc.strength = 2;
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chip->ecc.hwctl = tmio_nand_enable_hwecc;
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chip->ecc.calculate = tmio_nand_calculate_ecc;
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chip->ecc.correct = tmio_nand_correct_data;
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return 0;
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}
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static const struct nand_controller_ops tmio_ops = {
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.attach_chip = tmio_attach_chip,
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};
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static int tmio_probe(struct platform_device *dev)
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{
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struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
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struct resource *fcr = platform_get_resource(dev,
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IORESOURCE_MEM, 0);
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struct resource *ccr = platform_get_resource(dev,
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IORESOURCE_MEM, 1);
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int irq = platform_get_irq(dev, 0);
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struct tmio_nand *tmio;
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struct mtd_info *mtd;
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struct nand_chip *nand_chip;
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int retval;
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if (data == NULL)
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dev_warn(&dev->dev, "NULL platform data!\n");
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tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
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if (!tmio)
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return -ENOMEM;
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init_completion(&tmio->comp);
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tmio->dev = dev;
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platform_set_drvdata(dev, tmio);
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nand_chip = &tmio->chip;
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mtd = nand_to_mtd(nand_chip);
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mtd->name = "tmio-nand";
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mtd->dev.parent = &dev->dev;
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nand_controller_init(&tmio->controller);
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tmio->controller.ops = &tmio_ops;
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nand_chip->controller = &tmio->controller;
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tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
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if (!tmio->ccr)
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return -EIO;
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tmio->fcr_base = fcr->start & 0xfffff;
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tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
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if (!tmio->fcr)
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return -EIO;
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retval = tmio_hw_init(dev, tmio);
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if (retval)
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return retval;
|
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|
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/* Set address of NAND IO lines */
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nand_chip->legacy.IO_ADDR_R = tmio->fcr;
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nand_chip->legacy.IO_ADDR_W = tmio->fcr;
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|
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/* Set address of hardware control function */
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nand_chip->legacy.cmd_ctrl = tmio_nand_hwcontrol;
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nand_chip->legacy.dev_ready = tmio_nand_dev_ready;
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nand_chip->legacy.read_byte = tmio_nand_read_byte;
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nand_chip->legacy.write_buf = tmio_nand_write_buf;
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nand_chip->legacy.read_buf = tmio_nand_read_buf;
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if (data)
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nand_chip->badblock_pattern = data->badblock_pattern;
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|
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/* 15 us command delay time */
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nand_chip->legacy.chip_delay = 15;
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|
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retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
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dev_name(&dev->dev), tmio);
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if (retval) {
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dev_err(&dev->dev, "request_irq error %d\n", retval);
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goto err_irq;
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}
|
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|
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tmio->irq = irq;
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nand_chip->legacy.waitfunc = tmio_nand_wait;
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|
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/* Scan to find existence of the device */
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retval = nand_scan(nand_chip, 1);
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if (retval)
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goto err_irq;
|
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|
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/* Register the partitions */
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retval = mtd_device_parse_register(mtd,
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data ? data->part_parsers : NULL,
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NULL,
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data ? data->partition : NULL,
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data ? data->num_partitions : 0);
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if (!retval)
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return retval;
|
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|
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nand_cleanup(nand_chip);
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|
|
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err_irq:
|
|
tmio_hw_stop(dev, tmio);
|
|
return retval;
|
|
}
|
|
|
|
static int tmio_remove(struct platform_device *dev)
|
|
{
|
|
struct tmio_nand *tmio = platform_get_drvdata(dev);
|
|
struct nand_chip *chip = &tmio->chip;
|
|
int ret;
|
|
|
|
ret = mtd_device_unregister(nand_to_mtd(chip));
|
|
WARN_ON(ret);
|
|
nand_cleanup(chip);
|
|
tmio_hw_stop(dev, tmio);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int tmio_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
const struct mfd_cell *cell = mfd_get_cell(dev);
|
|
|
|
if (cell->suspend)
|
|
cell->suspend(dev);
|
|
|
|
tmio_hw_stop(dev, platform_get_drvdata(dev));
|
|
return 0;
|
|
}
|
|
|
|
static int tmio_resume(struct platform_device *dev)
|
|
{
|
|
const struct mfd_cell *cell = mfd_get_cell(dev);
|
|
|
|
/* FIXME - is this required or merely another attack of the broken
|
|
* SHARP platform? Looks suspicious.
|
|
*/
|
|
tmio_hw_init(dev, platform_get_drvdata(dev));
|
|
|
|
if (cell->resume)
|
|
cell->resume(dev);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
#define tmio_suspend NULL
|
|
#define tmio_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver tmio_driver = {
|
|
.driver.name = "tmio-nand",
|
|
.driver.owner = THIS_MODULE,
|
|
.probe = tmio_probe,
|
|
.remove = tmio_remove,
|
|
.suspend = tmio_suspend,
|
|
.resume = tmio_resume,
|
|
};
|
|
|
|
module_platform_driver(tmio_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
|
|
MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
|
|
MODULE_ALIAS("platform:tmio-nand");
|