271 lines
7.4 KiB
C
271 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* drivers/mmc/host/sdhci-of-sparx5.c
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*
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* MCHP Sparx5 SoC Secure Digital Host Controller Interface.
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*
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* Copyright (c) 2019 Microchip Inc.
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*
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* Author: Lars Povlsen <lars.povlsen@microchip.com>
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*/
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#include <linux/sizes.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/of_device.h>
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#include <linux/mfd/syscon.h>
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#include <linux/dma-mapping.h>
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#include "sdhci-pltfm.h"
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#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
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#define MSHC_DLY_CC_MASK GENMASK(16, 13)
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#define MSHC_DLY_CC_SHIFT 13
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#define MSHC_DLY_CC_MAX 15
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#define CPU_REGS_PROC_CTRL (0x2C * 4)
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#define ACP_CACHE_FORCE_ENA BIT(4)
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#define ACP_AWCACHE BIT(3)
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#define ACP_ARCACHE BIT(2)
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#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
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#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
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#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
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#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
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#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
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#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
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struct sdhci_sparx5_data {
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struct sdhci_host *host;
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struct regmap *cpu_ctrl;
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int delay_clock;
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};
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#define BOUNDARY_OK(addr, len) \
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((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
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/*
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* If DMA addr spans 128MB boundary, we split the DMA transfer into two
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* so that each DMA transfer doesn't exceed the boundary.
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*/
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static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
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dma_addr_t addr, int len,
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unsigned int cmd)
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{
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int tmplen, offset;
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if (likely(!len || BOUNDARY_OK(addr, len))) {
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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return;
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}
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pr_debug("%s: write_desc: splitting dma len %d, offset %pad\n",
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mmc_hostname(host->mmc), len, &addr);
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offset = addr & (SZ_128M - 1);
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tmplen = SZ_128M - offset;
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sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
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addr += tmplen;
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len -= tmplen;
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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}
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static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
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pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
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/* Update ACP caching attributes in HW */
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regmap_update_bits(sdhci_sparx5->cpu_ctrl,
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CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
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}
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static void sparx5_set_delay(struct sdhci_host *host, u8 value)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
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pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
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/* Update DLY_CC in HW */
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regmap_update_bits(sdhci_sparx5->cpu_ctrl,
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CPU_REGS_GENERAL_CTRL,
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MSHC_DLY_CC_MASK,
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(value << MSHC_DLY_CC_SHIFT));
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}
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static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
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{
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if (!mmc_card_is_removable(host->mmc)) {
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u8 value;
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value = sdhci_readb(host, MSHC2_EMMC_CTRL);
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if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
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value |= MSHC2_EMMC_CTRL_IS_EMMC;
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pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
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mmc_hostname(host->mmc), value);
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sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
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}
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}
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}
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static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
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{
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u8 value;
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pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
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value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
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~MSHC2_EMMC_CTRL_EMMC_RST_N;
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sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
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/* For eMMC, minimum is 1us but give it 10us for good measure */
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usleep_range(10, 20);
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sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
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MSHC2_EMMC_CTRL);
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/* For eMMC, minimum is 200us but give it 300us for good measure */
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usleep_range(300, 400);
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}
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static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
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{
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pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
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sdhci_reset(host, mask);
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/* Be sure CARD_IS_EMMC stays set */
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sdhci_sparx5_set_emmc(host);
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}
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static const struct sdhci_ops sdhci_sparx5_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.reset = sdhci_sparx5_reset,
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.adma_write_desc = sdhci_sparx5_adma_write_desc,
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};
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static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
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.quirks = 0,
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.quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
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SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
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.ops = &sdhci_sparx5_ops,
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};
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static int sdhci_sparx5_probe(struct platform_device *pdev)
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{
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int ret;
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const char *syscon = "microchip,sparx5-cpu-syscon";
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_sparx5_data *sdhci_sparx5;
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struct device_node *np = pdev->dev.of_node;
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u32 value;
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u32 extra;
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host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
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sizeof(*sdhci_sparx5));
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if (IS_ERR(host))
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return PTR_ERR(host);
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/*
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* extra adma table cnt for cross 128M boundary handling.
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*/
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extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
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if (extra > SDHCI_MAX_SEGS)
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extra = SDHCI_MAX_SEGS;
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host->adma_table_cnt += extra;
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pltfm_host = sdhci_priv(host);
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sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
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sdhci_sparx5->host = host;
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pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(pltfm_host->clk)) {
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ret = PTR_ERR(pltfm_host->clk);
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dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
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goto free_pltfm;
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}
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ret = clk_prepare_enable(pltfm_host->clk);
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if (ret)
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goto free_pltfm;
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if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
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(value > 0 && value <= MSHC_DLY_CC_MAX))
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sdhci_sparx5->delay_clock = value;
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sdhci_get_of_property(pdev);
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto err_clk;
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sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
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if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
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dev_err(&pdev->dev, "No CPU syscon regmap !\n");
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ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
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goto err_clk;
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}
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if (sdhci_sparx5->delay_clock >= 0)
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sparx5_set_delay(host, sdhci_sparx5->delay_clock);
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if (!mmc_card_is_removable(host->mmc)) {
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/* Do a HW reset of eMMC card */
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sdhci_sparx5_reset_emmc(host);
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/* Update EMMC_CTRL */
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sdhci_sparx5_set_emmc(host);
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/* If eMMC, disable SD and SDIO */
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host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
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}
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ret = sdhci_add_host(host);
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if (ret)
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goto err_clk;
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/* Set AXI bus master to use un-cached access (for DMA) */
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if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
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IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
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sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
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pr_debug("%s: SDHC version: 0x%08x\n",
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mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
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pr_debug("%s: SDHC type: 0x%08x\n",
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mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
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return ret;
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err_clk:
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clk_disable_unprepare(pltfm_host->clk);
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free_pltfm:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static const struct of_device_id sdhci_sparx5_of_match[] = {
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{ .compatible = "microchip,dw-sparx5-sdhci" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
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static struct platform_driver sdhci_sparx5_driver = {
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.driver = {
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.name = "sdhci-sparx5",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = sdhci_sparx5_of_match,
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.pm = &sdhci_pltfm_pmops,
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},
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.probe = sdhci_sparx5_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_sparx5_driver);
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MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
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MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
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MODULE_LICENSE("GPL v2");
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